Toshiba Memory Corporation

Koji Matsuo

Tatsuro Shinozaki

Yoshiaki Asao

Jun Fujiki

Kunifumi Suzuki

Takashi Ishida

Taishi Ishikura

Gaku Sudo

Jun Nogami

Kenzo Manabe

Masanobu Baba

Daisuke Kawamura

According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

Semiconductor device

According to one embodiment, an imprint pattern forming method includes providing a substrate with a pattern formation region and a peripheral region, the peripheral region having a surface lower than a surface of the pattern formation region, located at a periphery of the pattern formation region. The method includes forming an auxiliary pattern with a predetermined height on at least a portion of the peripheral region, providing a resist layer on at least the pattern formation region, and imprinting the resist layer using a template by locating the template in a region which includes a portion of the pattern formation region and a portion of the peripheral region.

Pattern forming method

According to an embodiment, a non-volatile memory device includes a first interconnection, a second interconnection closest to the first interconnection in a first direction, rectifying portions arranged in the first direction between the first interconnection and the second interconnection, and a first resistance change portion arranged between adjacent ones of the rectifying portions in the first direction. Each of the rectifying portions includes a first metal oxide layer and a second metal oxide layer.

Non-volatile memory device

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Koji Matsuo