Hyogo, Japan

Kiyoaki Morita

This inventor holds 3 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp.. Active years: 2003-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kiyoaki Morita. Retrieved from https://idiyas.com/inventor/kiyoaki-morita

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 33.3

Average Co-Inventor Count = 2.0

ph-index = 3

Forward Citations = 39(Granted Patents)


Company Filing History:


Years Active: 2003-2004

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3 patents (USPTO):Explore Patents

Title: Kiyoaki Morita: Innovator in Semiconductor Technology

Introduction

Kiyoaki Morita is a prominent inventor based in Hyogo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on improving the reliability and efficiency of semiconductor devices.

Latest Patents

Morita's latest patents include innovative designs for semiconductor devices that address common manufacturing challenges. One of his patents describes a semiconductor device that has structures designed to avoid deterioration caused by the manufacturing process. This device restricts the antenna effect without complicating the manufacturing process. Additionally, he has developed a semiconductor device that ensures matching characteristics of pairing transistors, along with a manufacturing method for such devices. This design includes an interconnection placed on an insulating film that covers a gate electrode and a semiconductor substrate, electrically connecting to the gate electrode. Furthermore, his work features a dummy transistor formed on the semiconductor substrate, which lacks the interconnection required for a typical transistor, yet is connected to the source/drain region of the dummy transistor.

Another notable patent involves a semiconductor device with a Metal-Insulator-Metal (MIM) capacitance element. In this design, a lower metal layer is provided on a lower interlayer insulating film within the MIM capacitance element forming region. The lower metal layer is created using the same process as the lower interconnection layer. A dielectric layer and an upper metal layer, patterned with the same mask, are placed on the lower metal layer. The upper metal layer is thinner than the lower metal layer, enhancing the reliability and lifespan of the MIM capacitance element through improved structural design and manufacturing steps.

Career Highlights

Throughout his career, Kiyoaki Morita has worked with notable companies in the semiconductor industry, including Mitsubishi Electric Corporation and Renesas Technology Corporation. His experience in these organizations has allowed him to refine his expertise and contribute to groundbreaking advancements in semiconductor technology.

Collaborations

Morita has collaborated with esteemed colleagues such as Kenji Yoshiyama and Motoshige Igarashi. Their combined efforts have further propelled innovation in the semiconductor field.

Conclusion

Kiyoaki Morita's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence the development of reliable and efficient semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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