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For the Inventor, By the Inventor

Kiran Chand Veernapu

Bengaluru, India

Kiran Chand Veernapu

This inventor holds 77 USPTO granted patents and 10 published patent applications and 6 EPO patents, primarily in Graphics Processing (CPC class G06F). Top assignee: Intel Corporation. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kiran Chand Veernapu. Retrieved from https://idiyas.com/inventor/kiran-chand-veernapu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 77 

% Patents Active = 94.8

 

Average Co-Inventor Count = 5.9

ph-index = 4

Forward Citations = 79(Granted Patents)

Forward Citations (Not Self Cited) = 60(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal77 out of 56,365 
 
Intel Corporation
 patents

Years Active: 2017-2026

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Areas of Expertise:
Graphics Processor
Power Management
Cache Allocation
Data Compression
Render Rate
Interconnect Fabric
Hybrid Graphics Units
Memory Access
Dynamic Allocation
Thread Scheduling
Bandwidth Consumption
Error Correction
77 patents (USPTO):Explore Patents
1. 12754597 - Processor power management (2026-10-06),
2. 12579072 - Graphics processor register file including a low energy portion and a high capacity portion (2026-03-17),
3. 12436727 - Regional adjustment of render rate (2025-10-07),
4. 12346189 - Interconnect fabric link width reduction to reduce instantaneous power consumption (2025-07-01),
5. 12198220 - Dynamic allocation of cache based on instantaneous bandwidth consumption at computing devices (2025-01-14),
6. 12124310 - Processor power management (2024-10-22),
7. 12118756 - Smart compression/decompression schemes for efficiency and superior results (2024-10-15),
8. 12061831 - Regional adjustment of render rate (2024-08-13),
9. 12050502 - Interconnect fabric link width reduction to reduce instantaneous power consumption (2024-07-30),
10. 12001344 - Memory access compression using clear code for tile pixels (2024-06-04),
11. 11868264 - Sector cache for compression (2024-01-09),
12. 11816384 - Regional adjustment of render rate (2023-11-14),
13. 11762696 - Hybrid low power homogenous grapics processing units (2023-09-19),
14. 11733758 - Processor power management (2023-08-22),
15. 11681349 - Interconnect fabric link width reduction to reduce instantaneous power consumption (2023-06-20),

Title: Kiran Chand Veernapu - Pioneering Inventor from Bengaluru

Introduction: Kiran Chand Veernapu is a renowned inventor hailing from Bengaluru, India, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Kiran Chand Veernapu holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his continuous commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Kiran Chand Veernapu has worked with leading tech companies and research institutions, where he has spearheaded numerous projects that have revolutionized the industry.

Collaborations: Throughout his career, Kiran Chand Veernapu has collaborated with top researchers, engineers, and scientists from around the globe, fostering a culture of innovation and knowledge sharing.

Conclusion: Kiran Chand Veernapu's relentless passion for innovation and his remarkable contributions to the field make him a true pioneer in the world of technology, inspiring the next generation of inventors and innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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