The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2024
Filed:
Feb. 13, 2023
Intel Corporation, Santa Clara, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
David Puffer, Tempe, AZ (US);
Prasoonkumar Surti, Folsom, CA (US);
Lakshminarayanan Striramassarma, El Dorado Hills, CA (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Kiran C. Veernapu, Bangalore, IN;
Balaji Vembu, Folsom, CA (US);
Pattabhiraman K, Bangalore, IN;
Intel Corporation, Santa Clara, CA (US);
Abstract
One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.