The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

May. 07, 2024
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mohammed Tameem, Bangalore, IN;

Altug Koker, El Dorado Hills, CA (US);

Kiran C. Veernapu, Bangalore, IN;

Abhishek R. Appu, El Dorado Hills, CA (US);

Ankur N. Shah, Folsom, CA (US);

Joydeep Ray, Folsom, CA (US);

Travis T. Schluessler, Hillsboro, OR (US);

Jonathan Kennedy, Bristol, GB;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3234 (2019.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3253 (2013.01); G06F 1/3206 (2013.01); G06F 1/324 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 13/1678 (2013.01); G06F 13/4022 (2013.01);
Abstract

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.


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