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For the Inventor, By the Inventor

Tamamura, Japan

Kinya Mitsumoto

This inventor holds 26 USPTO granted patents, primarily in Semiconductor Technology. Top assignees: Hitachi, Ltd., Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.. Active years: 1987-2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kinya Mitsumoto. Retrieved from https://idiyas.com/inventor/kinya-mitsumoto

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 26

% Patents Active = 88.5

Average Co-Inventor Count = 3.5

ph-index = 9

Forward Citations = 291(Granted Patents)


Location History:

  • Ohme, JP (1987 - 1988)
  • Koganei, JP (1987 - 1991)
  • Tokyo, JP (1991 - 1994)
  • Takasaki, JP (1995)
  • Tanamura-machi, JP (1997)
  • Tamamuramachi, JP (1995 - 1999)
  • Tmamura, JP (2003 - 2007)
  • Tamamura, JP (1997 - 2009)

Company Filing History:

goldMedal16 out of 42,743 
 
Hitachi, Ltd.
 patents
silverMedal9 out of 3,781 
 
Renesas Technology Corp.
 patents
bronzeMedal3 out of 336 
 
Hitachi Ulsi Systems Co., Ltd.
 patents
4. 2 out of 149 
 
Hitachi Microcomputer Engineering, Ltd.
 patents
5. 1 out of 14 
 
Hitachi Haramachi Semi-Conductor, Ltd.
 patents
6. 1 out of 834,601 
Other
 patents
where one patent can have more than one assignee

Years Active: 1987-2009

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Areas of Expertise:
Semiconductor Device
Semiconductor Memory Device
Synchronization Circuit
Data Processing System
High-Speed Memory
Double Data Rate
Logic Gate Circuit
Pipelined Write Operation
Reference Current Generator
Redundant Cells
Variable Delay Lines
Write Circuit
26 patents (USPTO):Explore Patents
1. 7623397 - Semiconductor device (2009-11-24),
2. 7397880 - Synchronization circuit and synchronization method (2008-07-08),
3. 7254068 - Semiconductor memory device (2007-08-07),
4. 7196424 - Semiconductor device (2007-03-27),
5. 7068551 - Semiconductor memory device (2006-06-27),
6. 6909312 - Synchronization circuit and synchronization method (2005-06-21),
7. 6856559 - Semiconductor memory device (2005-02-15),
8. 6770941 - Semiconductor device and method of manufacturing a semiconductor device (2004-08-03),
9. 6725325 - Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function (2004-04-20),
10. 6625070 - Semiconductor memory device (2003-09-23),
11. 5920510 - Semiconductor device capable of holding signals independent of the pulse (1999-07-06),
12. 5761150 - Synchronous memory with pipelined write operation (1998-06-02),
13. 5734616 - Semiconductor memory device and sense circuit (1998-03-31),
14. 5654931 - High-speed semiconductor memory device and data processing system using (1997-08-05),
15. 5646897 - Logic gate circuit and parallel bit test circuit for semiconductor (1997-07-08),

Title: The Innovative Journey of Kinya Mitsumoto

Introduction: Kinya Mitsumoto, a talented inventor hailing from Tamamura, Japan, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Kinya Mitsumoto holds several patents in the areas of robotics, artificial intelligence, and renewable energy technologies, showcasing his diverse range of expertise and creativity.

Career Highlights: With a career spanning over two decades, Kinya Mitsumoto has worked with leading tech companies in Japan, spearheading research and development projects that have led to cutting-edge inventions and solutions.

Collaborations: Throughout his career, Kinya Mitsumoto has collaborated with top researchers, engineers, and scientists both locally and internationally, fostering a culture of innovation and knowledge sharing.

Conclusion: Kinya Mitsumoto's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and technologists worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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