Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Other

Hitachi Haramachi Semi-conductor, Ltd.

Kinya Mitsumoto

Takashi Akioka

Noboru Akiyama

Yoshiaki Yazawa

Masao Shinozaki

Shinji Nakazato

Masahiro Iwamura

Masanori Odaka

Hideaki Uchida

Hiroki Ueno

Akihisa Aoyama

Nobuaki Miyakawa

Seigoh Yukutake

Yutaka Kobayashi

Akihiko Emori

Katsumi Ogiue

Seigou Yukutake

Satoru Isomura

Shuichi Miyaoka

Masamori Kashiyama

Hiroshi Murayama

Kazuhiro Akimoto

Masami Usami

Hitoshi Abe

Noriyuki Itano

Yoshikuni Kobayashi

Tatsumi Yamauchi

Hideo Maejima

Takahiro Nagano

Akihiro Tamba

Hiroki Miyashita

Sadayuki Ohkuma

Masahiko Nishiyama

Shuko Yamauchi

Kazunori Onozawa

Hideto Kazama

Tomoyuki Someya

Shoichi Ozeki

Yoshikazu Iida

Takeshi Agari

A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.

Semiconductor device

In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the phase from the first pulse. The reference pulse and the first pulse are compared by a first phase comparing circuit, and the reference pulse, second pulse and third pulse are compared by a second phase comparing circuit. A control voltage generating circuit forms a control voltage by giving priority to a comparison output of the second phase comparing circuit against a comparison output of the first phase comparing circuit. Delay time of the first variable delay circuit is controlled after the phases are matched by forming the control voltage with the comparison output of the first phase comparing circuit.

Synchronization circuit and synchronization method

Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Semiconductor memory device

Phase synchronization is achieved by forming a first pulse to be synchronized with a reference pulse, a second pulse leading in phase for a certain period relative to said first pulse and a third pulse delayed in phase for a certain period from said first pulse; comparing said reference pulse with said first pulse in a first comparing; comparing said reference pulse with said second pulse and said third pulse in a second comparing; and forming a control voltage by giving priority to a comparison output of said second comparing with respect to a comparison output of said first comparing, matching the phase of said reference pulse with the phrase of said second pulse or said third pulse, and matching, after said matching of phases, the phrase of said reference pulse with the phase of said first pulse by forming said control, voltage from the comparison output of said first comparing.

The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.

Semiconductor device and method of manufacturing a semiconductor device

A semiconductor memory device having a double data rate (DDR) mode includes a first comparison logic circuit comparing the lower bits of a specified memory address for a reading operation with the lower bits of a specified memory address for a preceding writing operation, a second comparison logic circuit detecting if bits other than the lower bits match, and a third comparison logic circuit detecting that, when a match is obtained from the second comparison logic circuit, the lower bits of the specified memory address or a secondary memory address such as a burst address for the reading operation match the lower bits of the specified memory address or secondary memory address for the preceding writing operation. The device may have a late write function and a register may be provided to latch single data rate (SDR)/DDR mode information.

Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function

A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.

Semiconductor device capable of holding signals independent of the pulse

There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

Synchronous memory with pipelined write operation

A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

Semiconductor memory device and sense circuit

A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved. Another feature is that either the input/output pads of the data into or out of the semiconductor integrated circuit device or their accompanying circuit units are distributed in the semiconductor integrated circuit device. The individual features described above can be used solely or in combination, if necessary, to achieve the above-specified objects.

High-speed semiconductor memory device and data processing system using

A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

Logic gate circuit and parallel bit test circuit for semiconductor

Growing community of inventors

Tamamura, Japan

Kinya Mitsumoto