Tokyo, Japan

Katsumi Nakamura

This inventor holds 87 USPTO granted patents and 12 published patent applications, plus 3 CIPO patents and 4 EPO patents, primarily in Semiconductor Devices (CPC class H01L29-7397). Top assignees: Mitsubishi Electric Corporation, Mitsubishi Denki Kabushiki Kaisha, Calsonic Kansei Corporation. Active years: 1996-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Katsumi Nakamura. Retrieved from https://idiyas.com/inventor/katsumi-nakamura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 87 

% Patents Active = 85.1

 

 

Average Co-Inventor Count = 1.9

ph-index = 15

Forward Citations = 658(Granted Patents)

Forward Citations (Not Self Cited) = 574(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Osaka, JP (1996)
  • Itami, JP (1996 - 1998)
  • Kanagawa, JP (2004)
  • Sanda, JP (2000 - 2006)
  • Hyogo, JP (1999 - 2009)
  • Chiyoda-ku, JP (2003 - 2020)
  • Tokyo, JP (1999 - 2024)

Company Filing History:


Years Active: 1996-2026

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Areas of Expertise:
Power Semiconductor Device
Manufacturing Method
Buffer Layer
Trench Structure
Diode
Electric Field Buffer Layer
Hollow Engine Valve
Conductivity Types
Robot Control System
Assembly Body Manufacturing
87 patents (USPTO):Explore Patents

Title: The Innovative Journey of Katsumi Nakamura in Semiconductor Technology

Introduction: Katsumi Nakamura is a renowned inventor based in Tokyo, Japan, celebrated for his groundbreaking contributions to semiconductor technology. With an impressive portfolio of 82 patents, he has made a significant impact in the field, particularly through his inventive methodologies and device designs.

Latest Patents: Katsumi Nakamura’s recent patents highlight his expertise in semiconductor devices and manufacturing processes. One of his notable inventions is a semiconductor device that comprises a semiconductor substrate, a drift layer of first conductivity type, accompanied by a buffer layer of the same conductivity type. Notably, his innovation includes both a first and a second semiconductor layer, arranged in a specific orientation relative to the substrate, where the second layer has a higher level of impurities. Another significant patent features a semiconductor device that integrates an N-drift layer and a P base layer, further innovating through the development of unique buffer layers with distinct impurity characteristics, showcasing his mastery in semiconductor structures.

Career Highlights: Throughout his distinguished career, Katsumi Nakamura has worked with leading organizations in the electronics and manufacturing sectors, including Mitsubishi Electric Corporation and Mitsubishi Denki Kabushiki Kaisha. His roles have allowed him to steer innovative projects and contribute to industry advancements.

Collaborations: Katsumi has collaborated with various professionals in the field, including notable colleagues like Tadaharu Minato and Ze Chen. These partnerships have facilitated the exchange of ideas and enabled groundbreaking collaborative projects that push the boundaries of semiconductor technology.

Conclusion: Katsumi Nakamura's work exemplifies the spirit of innovation in the semiconductor industry. Through his extensive patents and collaborations, he has not only advanced technology but has also inspired future generations of inventors and engineers. His contributions continue to influence the landscape of semiconductor manufacturing and design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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