Kai-Jen Ko

Title: Innovations and Contributions of Inventor Kai-Jen Ko

Introduction

Kai-Jen Ko is a notable inventor based in Hsin-Chu, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on improving testing methods and reducing biases in semiconductor devices.

Latest Patents

One of his latest patents is titled "Universal test platform and test method for latch-up." This invention provides a method for testing the latch-up phenomenon of a chip. The chip is tested on a platform that stores a test program specifically designed for this purpose. The method involves several steps, including obtaining the test program, acquiring pin data, setting an initial value for an input pin, and measuring the current to determine if it exceeds a predetermined value. Another significant patent is the "Method for reducing gate length bias." This method employs an additional blanket ion implantation process to adjust the etching properties of the undoped conductive layer. By using a polysilicon layer to form NMOS and PMOS gate electrodes, the gate length bias between these electrodes can be effectively minimized.

Career Highlights

Throughout his career, Kai-Jen Ko has worked with prominent companies in the semiconductor industry, including United Microelectronics Corporation and Faraday Technology Corporation. His experience in these organizations has allowed him to develop innovative solutions that address critical challenges in semiconductor manufacturing.

Collaborations

He has collaborated with notable colleagues such as Yuan-Li Tsai and Kuo-Hua Ho, contributing to advancements in their respective fields.

Conclusion

Kai-Jen Ko's innovative patents and career achievements highlight his significant impact on semiconductor technology. His work continues to influence the industry and pave the way for future advancements.