Hsinchu, Taiwan

Jui-Hsiang Pan

This inventor holds 35 USPTO granted patents, primarily in CMOS Sensors. Top assignee: United Microelectronics Corp.. Active years: 2000-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jui-Hsiang Pan. Retrieved from https://idiyas.com/inventor/jui-hsiang-pan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.3

ph-index = 10

Forward Citations = 328(Granted Patents)


Location History:

  • Hsnichu, TW (2007)
  • Hsin-Chu, TW (2000 - 2010)

Company Filing History:


Years Active: 2000-2010

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Areas of Expertise:
CMOS Sensor
Image Sensor
Photodiode
Semiconductor Packaging
Electrostatic Discharge
Flexible Wiring Substrate
Quad Flat No-Lead
Photosensitive Module
Photodetector Pixel Cell
High Voltage Protection
Manufacturing Method
Silicon Chip Inductor
35 patents (USPTO):Explore Patents

Title: Innovations by Jui-Hsiang Pan: A Pioneer in Semiconductor Packaging

Introduction

Jui-Hsiang Pan, based in Hsinchu, Taiwan, is a distinguished inventor with an impressive portfolio of 35 patents. His contributions to the field of semiconductor technology have been instrumental in advancing packaging methodologies, greatly impacting the efficiency and effectiveness of electronic devices.

Latest Patents

Among Jui-Hsiang Pan's latest innovations, the "Package of a Semiconductor Device with a Flexible Wiring Substrate and Method for the Same" stands out. This invention presents a novel package that includes a semiconductor substrate with at least one pad, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate that is electrically connected to the bump via the adhesive layer. This design allows for a direct conductive attachment of the flexible wiring substrate to the semiconductor substrate, resulting in a reduction in package size and manufacturing costs.

Another notable patent is the "Manufacturing Method of a Quad Flat No-Lead Package Structure." This innovative method involves creating a quad flat no-lead package structure that comprises a chip carrier and at least one chip. The chip is positioned on the top surface of the chip carrier, which is designed with multiple flat no-lead conductive leads as I/O pads for external circuitry. The method accommodates various technologies, including wiring bonding, flip chip, and surface mount technologies, ensuring flexibility in the manufacturing process.

Career Highlights

Jui-Hsiang Pan is currently associated with United Microelectronics Corporation (UMC), where he focuses on cutting-edge semiconductor packaging techniques. His extensive knowledge and creativity have allowed him to contribute significantly to UMC's technological advancements in the industry.

Collaborations

Throughout his career, Pan has collaborated with esteemed colleagues such as Cheng-Kuang Sun and Kuang-Shin Lee. These partnerships have fostered an environment of innovation, leading to breakthroughs in semiconductor packaging and processes.

Conclusion

With a robust portfolio and a commitment to innovation, Jui-Hsiang Pan continues to be a pivotal figure in the semiconductor industry. His developments not only enhance the efficiency of devices but also pave the way for future technologies that can further revolutionize the field. As he continues to explore new avenues in semiconductor packaging, the impact of his work will likely resonate for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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