United Microelectronics Corp.

Jui-Hsiang Pan

Cheng-Kuang Sun

Kuang-Shin Lee

Ming-I Chen

Kuang-Chih Cheng

Kevin Lee

Joseph Z Sun

Ming-Chieh Chen

Ming-Tsung Tung

Chih-Hua Lee

Jen-Yao Hsu

Kuang Yuan Lee

Cheng-Hung Chien

Pei-Yu Chiang

A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.

Package of a semiconductor device with a flexible wiring substrate and method for the same

The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.

Manufacturing method of a quad flat no-lead package structure

The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.

Quad flat no-lead package structure and manufacturing method thereof

A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.

Process for manufacturing semiconductor device

An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.

Image sensor and fabricating method thereof

Process for manufacturing photosensitive module

A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time, an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer. The second type lightly doped layer has a thickness much greater than the second type heavily doped layer.

Method of manufacturing photodiode CMOS image sensor

The surface of the semiconductor wafer includes a silicon substrate containing first-type dopants, a well of first-type dopants positioned in a predetermined region on the substrate, a photo diode positioned on the semiconductor wafer and comprising an active region positioned on the surface of the well, the active region being used to form a MOS transistor of second-type dopants, and an insulation layer positioned on the surface of the substrate surrounding a predetermined photo sensor, the photo sensor positioned beside the well. A first ion implantation process is performed to form a first doped region of second-type dopants on the surface of the photo sensor. A second ion implantation process is then performed to form a second doped region of second-type dopants inside the photo sensor. The second doped region is positioned under the first doped region, the dopant density of the second doped region is less than that of the first doped region, and the second doped region functions to reduce the electrical field around the first doped region so as to reduce leakage current.

Method of forming a photo sensor in a photo diode

An image sensor structure. A first PN photodiode is located in a photo-sensing region of a substrate. A second PN photodiode is located in the substrate above the first PN photodiode. An N-type terminal of the first PN photodiode connects to a source/drain region of a first transistor. A contact is coupled with the second PN photodiode. The contact connects to a gate of a second transistor.

Image sensor structure

A photodetector pixel cell is proposed by the invention. Herein, the presented pixel cell comprises a diode region and a circuit region, and is enclosed by isolation. Moreover, the doped region is existed inside both regions. The structure of the presented pixel cell comprises following characteristics: First, the first well is only located inside the circuit region, where the conductive type of the first well is opposite to the conductive type of the doped region. Second, the second well is located inside the diode region and is contiguous to the isolation, where the conductive type of the second well is equal to that of the doped region. Third, the doped region is not contiguous to the second well, they are separated by uncovered surface part of the substrate. Fourth, the doped region and the substrate provide the diode. Therefore, not only both the light sensitivity is increased and the RC delay time is decreased for both the scale of the PN-junction is increased and the width of the depletion region is increased, but also the damage induced leakage current is properly prevented for the edge of isolation is surrounded second well inside the diode region.

Photodetector pixel cell

A method of fabricating a MOS sensor is described. A P-doped region extending into a substrate is formed. A stacked polysilicon structure is formed over the P-doped region. Ions are implanted into the substrate to form an N-doped region extending shallowly into the P-doped region, the stacked polysilicon structure serving as an implantation buffer layer. The stacked polysilicon structure are patterned and etched to form a stacked polysilicon ring over the N-doped region. A metal line is formed for electrically connecting the stacked polysilicon ring with a gate of a MOS transistor.

Method of fabricating MOS sensor

The present invention relates to a photo diode and its method of formation. The photo diode comprises a photo sensor area positioned in a predetermined region on the substrate, and a dielectric area positioned on the substrate surrounding the photo sensor area. The dielectric area comprises a field oxide layer covering a portion of the dielectric area and at least one dummy active area surrounding the photo sensor area, and a narrow slot of the field oxide layer exists between each dummy active area and the photo sensor area. In the formation of the dielectric area, the dummy active area reduces the thickness of the field oxide layer in the slot and decreases the stress causes by the field oxide layer. So the leakage current of the photo diode in unlighted status can be decreased and improve the signal to noise ratio.

Photodiode with photosensor area laterally surrounded by field oxide and dummy active area regions

The present invention proposes a die seal ring. The provided die seal ring is formed on a substrate and is used to encompass a die by locating between the die and adjacent scribe lines. Moreover, the provided die seal ring comprises a plurality of dielectric layers and a plurality of metal structures, wherein any metal structure is not overlapped with other metal structures. Moreover, dielectric layers are located on the substrate in sequence, and each metal structure is stacked by one metal ring and one metal plug. In addition, any metal ring is located on a dielectric layer and is covered by another dielectric layer, and metal rings of different metal structures are located on different dielectric layers. Further, any metal plug is located in the dielectric layers and is used to connect the metal ring to the substrate. Of course, if the aspect ratio of any metal plug is too large to be properly formed, an appendant metal ring is used to reduce the aspect ration of the metal plug. Therefore, owing to the fact that any metal ring can directly connect to the substrate without application of another metal ring except the aspect ration is too large, the height of any metal structure can be efficiently reduced and then the height of the presented seal ring also can be efficiently reduced.

Die seal ring

A silicon chip built-in inductor structure. The structure at least includes a substrate, a plurality of active devices on the substrate, a dielectric layer with a planarized upper surface and an inductor device. The substrate can be divided into an active device region and a region containing grid-like field oxide devices. The grid-like field oxide region has a plurality of field oxide layers, a plurality of first-type-ion-doped regions underneath the field oxide layers and a plurality of second-type-ion-doped region in the substrate between the various field oxide layers. A plurality of junction regions are formed between the first-type-ion-doped regions and the second-type-ion-doped regions. The junction regions impede the flow of an eddy current along a prescribed direction. A dielectric layer is formed over the substrate covering the active devices and the field oxide devices. The inductor device is formed on the dielectric layer above the field oxide devices.

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Hsinchu, Taiwan

Jui-Hsiang Pan