This inventor holds 2 USPTO granted patents and 2 published patent applications. Top assignee: United Microelectronics Corp.. Active years: 2021-2023.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2021-2023
Title: Jui-Fa Lu: Semiconductor Layout and Structure Innovations
Introduction
Jui-Fa Lu is an inventor based in Tainan, Taiwan, and is associated with United Microelectronics Corporation. Lu’s work includes semiconductor design and structures involving resistor elements and dummy patterns. The provided information lists 2 patents.
Latest Patents
Lu’s listed patents address the placement and arrangement of dummy patterns in semiconductor layouts.
“Method of Dummy Pattern Layout” describes a computer-based design method for configuring dummy conductive structures in alignment with resistor elements. It also positions dummy support patterns between adjacent conductive structures, with each conductive structure equidistant from the support patterns on either side.
“Semiconductor Structure” describes a substrate with a resistor region containing isolation structures and dummy support patterns. Dummy conductive structures are placed on the isolation structures, equidistant from support patterns on both sides, while resistor elements are positioned above and aligned with the conductive structures.
Career Highlights
Lu’s listed work focuses on semiconductor layout design and structural arrangements intended to coordinate resistor elements, conductive structures, isolation structures, and support patterns. The patents reflect attention to precise spacing and alignment within integrated circuit designs.
Collaborations
The provided information names Chien-Nan Lin and Ching-Hua Yeh as Lu’s coworkers. Their specific roles in the listed patents are not stated.
Conclusion
Jui-Fa Lu’s listed patent work centers on carefully aligned dummy patterns and resistor elements in semiconductor designs, reflecting a focused contribution to integrated circuit layout and structure.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
