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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11545484 B1

PDFFull Text
Date of Patent:
Jan. 03, 2023

Filed:

Jan. 15, 2021

Method of dummy pattern layout

Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Jui-Fa Lu, Tainan, TW;

Chien-Nan Lin, Hsinchu, TW;

Ching-Hua Yeh, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsinchu, TW;

Attorney:

J.C. Patents

Primary Examiner:

Marcos D Pizarro

Assistant Examiner:

Quinton A Brasfield

Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 23/528 (2006.01); H01L 29/66 (2006.01); H01L 23/532 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 23/528 (2013.01); H01L 23/5228 (2013.01); H01L 23/53257 (2013.01); H01L 28/20 (2013.01); H01L 29/0649 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); G06F 2119/18 (2020.01);
Abstract

A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

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Lu, Jui-Fa. (2023). Method of dummy pattern layout (U.S. Patent No. 11545484). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11545484

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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