Joseph Neil Greeley

This inventor holds 34 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Technology. Top assignees: Micron Technology Incorporated, Lodestar Licensing Group LLC. Active years: 2009-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Joseph Neil Greeley. Retrieved from https://idiyas.com/inventor/joseph-neil-greeley

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 34 (Patent Applications = 2)

% Patents Active = 73.5

Average Co-Inventor Count = 3.7

ph-index = 7

Forward Citations = 143(Granted Patents)

Company Filing History:

32 out of 39,222

Micron Technology Incorporated

patents

1 out of 218

Lodestar Licensing Group LLC

patents

where one patent can have more than one assignee

Years Active: 2009-2025

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Areas of Expertise:

Pitch Reduction

Semiconductor Devices

Resistive RAM

Memory Cells

Capacitor Structures

Microelectronic Substrates

Particle Removal

Oxide Modification

Phase Change Memory

Programmable Transistors

Elevationally-Extending Strings

Non-Volatile Memory

34 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12463044 - Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same (2025-11-04),

2. 11935756 - Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same (2024-03-19),

3. 11335563 - Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same (2022-05-17),

4. 11139159 - Methods of removing particles from over semiconductor substrates (2021-10-05),

5. 10727242 - Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor (2020-07-28),

6. 10607844 - Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same (2020-03-31),

7. 10580782 - Methods of forming an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor (2020-03-03),

8. 10263007 - Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor (2019-04-16),

9. 10137481 - Methods of removing particles from over semiconductor substrates (2018-11-27),

10. 10096483 - Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same (2018-10-09),

11. 10014309 - Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor (2018-07-03),

12. 9761457 - Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same (2017-09-12),

13. 9666801 - Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array (2017-05-30),

14. 9634250 - Resistive RAM devices and methods (2017-04-25),

15. 9419219 - Resistive RAM devices and methods (2016-08-16),

Title: Joseph Neil Greeley: Innovator in Semiconductor Technology

Introduction

Joseph Neil Greeley, based in Boise, ID, is an accomplished inventor with a remarkable portfolio of 33 patents. His contributions primarily focus on advanced semiconductor technologies, demonstrating a consistent commitment to innovation in this highly competitive field.

Latest Patents

Greeley's latest inventions include groundbreaking methodologies centered on pitch reduction technology for semiconductor devices. One notable patent describes a method for patterning layers that enhances the density of features over an initial patterning layer through a series of self-aligned spacers. This innovative approach involves providing a layer to be etched and forming a sacrificial patterning layer via optical lithography. Depending on the specific embodiment, the patterning layer may undergo trimming, followed by the formation and etching of multiple spacer layers. The number of these layers and their specific dimensions are tailored to achieve the desired increase in feature density, ultimately enhancing the performance of in-process semiconductor devices and electronic systems.

Career Highlights

Greeley is currently associated with Micron Technology Incorporated, a leading American producer of computer memory and semiconductor devices. Throughout his career, he has focused on expanding the boundaries of semiconductor manufacturing processes, striving to improve efficiency and performance in electronic systems.

Collaborations

During his tenure at Micron, Greeley has collaborated with several esteemed colleagues, including Paul A. Morgan and John A. Smythe. These collaborations have contributed to the advancement of technologies in the semiconductor sector, showcasing the importance of teamwork in driving innovation.

Conclusion

Joseph Neil Greeley exemplifies the spirit of innovation in the semiconductor industry. His extensive patent portfolio not only reflects his technical expertise but also his dedication to pushing the limits of technology. As he continues to develop new methods and systems, Greeley's work remains pivotal in shaping the future of semiconductor devices.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

2 patents pending: