The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Feb. 23, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Wei Yeeng Ng, Boise, ID (US);

Ian Laboriante, Boise, ID (US);

Joseph Neil Greeley, Boise, ID (US);

Tom J. John, Boise, ID (US);

Ho Yee Hui, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11556 (2017.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/31111 (2013.01); H01L 21/31133 (2013.01); H01L 21/31138 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11582 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08);
Abstract

A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.


Find Patent Forward Citations

Loading…