Meridian, ID, United States of America

Jonathan S Hacker

This inventor holds 22 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Technology. Top assignees: Micron Technology Incorporated, Other. Active years: 2018-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jonathan S Hacker. Retrieved from https://idiyas.com/inventor/jonathan-s-hacker

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 100.0

Average Co-Inventor Count = 1.9

ph-index = 3

Forward Citations = 31(Granted Patents)


Company Filing History:

goldMedal20 out of 39,176 
 
Micron Technology Incorporated
 patents
silverMedal1 out of 834,453 
Other
 patents
where one patent can have more than one assignee

Years Active: 2018-2024

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Areas of Expertise:
Semiconductor Device
Electrochemical Plating
Die Bonding
Multi-layered Encapsulant
Testing Probe
Self-alignment
Passivation Material
Temporary Carrier
Cutting Blades
Debonding Techniques
Manufacturing Methods
Device Packages
22 patents (USPTO):Explore Patents

Title: Innovations of Jonathan S. Hacker: A Pioneer in Semiconductor Technology

Introduction

Jonathan S. Hacker, based in Meridian, ID, is a prominent inventor with a remarkable portfolio that includes 22 patents. His work primarily focuses on the advancement of semiconductor technology, contributing significantly to the field through innovative designs and methods.

Latest Patents

Among his latest inventions, Hacker has developed a semiconductor device that features a multi-layered encapsulant along with associated systems, devices, and methods. This innovative design comprises a substrate with traces protruding above its top surface, a prefill material over the substrate, a die attached to this substrate, and a wafer-level underfill that exists between the prefill material and the die.

Another notable patent addresses the uniform electrochemical plating of metal onto arrays of pillars with varying lateral densities. This technology involves a semiconductor die assembly featuring two separately spaced semiconductor dies. The design cleverly integrates an array of first and second pillars extending from different regions of the first semiconductor die, ensuring that their differing lateral densities and sizes optimize the metal deposition process during electrochemical plating.

Career Highlights

Hacker's career has been marked by significant contributions while working for leading technology companies, including Micron Technology Incorporated. His groundbreaking work in semiconductor device engineering has earned him recognition in the industry, attracting attention for his inventive approaches and solutions.

Collaborations

Throughout his career, Hacker has collaborated with esteemed colleagues in the field, including Shijian Luo and Christopher J. Gambee. Their combined expertise has further enhanced the innovation processes and outcomes of projects they have undertaken together, fostering an environment of creativity and technological advancement.

Conclusion

Jonathan S. Hacker stands as a notable figure in the world of semiconductor inventions, with a rich history of patents and collaborations. His contributions continue to shape the future of semiconductor technology, demonstrating the profound impact of inventive minds on advancing the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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