Micron Technology Incorporated

Other

Jonathan S Hacker

Shijian Luo

Chandra S Tiwari

Christopher J Gambee

Bret K Street

Wei Zhou

Tony M Lindenberg

Kurt J Bossart

Mayukhee Das

Zhaohui Ma

Aibin Yu

Sony Varghese

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

Semiconductor device with a multi-layered encapsulant and associated systems, devices, and methods

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

A dressing board for sharpening and/or shaping blades for manufacture of semiconductor devices can include a working surface configured to sharpen and/or shape a cutting surface of a dicing or edging blade for manufacture of a semiconductor device. The working surface can be configured to contact the cutting surface of the blade when sharpening or shaping the cutting surface. The dressing board can include a support substrate configured to support the working surface with respect to a floor of an enclosure in which the dressing board is positioned. In some embodiments, the working surface includes a first portion that is not parallel to the floor.

Systems and methods for forming semiconductor cutting/trimming blades

A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3D interconnect (3DI) structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

Inductive testing probe apparatus for testing semiconductor die and related systems and methods

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

Die features for self-alignment during die bonding

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

Semiconductor devices having discretely located passivation material, and associated systems and methods

A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3DI structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

Systems and methods for debonding a carrier from a semiconductor device are disclosed herein. In one embodiment, a system for debonding a carrier from a semiconductor device includes a support member positioned to carry the semiconductor device and a fluid delivery device having an exit positioned to direct a fluid toward an adhesive layer between the carrier and the semiconductor device. The fluid directed from the fluid delivery device initiates debonding of the carrier from the semiconductor device by weakening or loosening at least a portion of the adhesive. The system further includes a liftoff device configured to releasably engage the carrier and apply a debonding force to the carrier to complete debonding of the carrier from the semiconductor device.

Growing community of inventors

Meridian, ID, United States of America

Jonathan S Hacker