Hillsboro, OR, United States of America

Jonathan Cannon Hall

This inventor holds 29 USPTO granted patents and 4 published patent applications and 3 EPO patents, primarily in Data Processing. Top assignee: Intel Corporation. Active years: 2013-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jonathan Cannon Hall. Retrieved from https://idiyas.com/inventor/jonathan-cannon-hall

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29 

% Patents Active = 82.8

 

Average Co-Inventor Count = 5.6

ph-index = 6

Forward Citations = 107(Granted Patents)


Location History:

  • Hiullsboro, OR (US) (2016)
  • Portland, OR (US) (2016 - 2018)
  • Hillsboro, OR (US) (2013 - 2024)

Company Filing History:


Years Active: 2013-2026

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Areas of Expertise:
Gather/Scatter Operations
Vector Instructions
Cache Management
Processor Efficiency
Data Elements
Clock Gating
Memory Access
Architectural Register State
Memory Fault Suppression
Coalescing
Instruction Format
Data Tracking
29 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Jonathan Cannon Hall

Introduction: Jonathan Cannon Hall is a prominent inventor based in Hillsboro, Oregon, known for his extensive contributions to technology with a remarkable portfolio of 27 patents. His work at Intel Corporation has paved the way for advancements in processing and computational efficiency.

Latest Patents: One of Jonathan's latest patents is centered around a "Vector Friendly Instruction Format and Execution Thereof." This invention presents a novel instruction set configuration that enhances the performance of processors. The vector-friendly instruction format is designed with multiple fields, including a base operation field, a modifier field, an augmentation operation field, and a data element width field. This innovative format supports different versions of base operations and augmentation operations, allowing flexibility through varied values in the defined fields. The design aims to optimize instruction streams by ensuring that only one value can occupy each field at any instruction occurrence, thus improving execution efficiency.

Career Highlights: Throughout his career at Intel Corporation, Jonathan has made significant strides in technology development. His expertise in designing instruction sets has been pivotal in enhancing computational capabilities, positioning him as a leader in the field of computer architecture.

Collaborations: Jonathan's professional journey includes collaboration with esteemed colleagues such as Andrew Thomas Forsyth and Christopher J Hughes. These partnerships have fostered an environment of innovation, leading to the successful development of complex technologies and advancing their collective expertise in the field.

Conclusion: Jonathan Cannon Hall's contributions to technology through his numerous patents underscore his dedication and innovative spirit. His latest work on vector-friendly instruction formats showcases the potential for improved processing efficiency and sets a strong foundation for future advancements in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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