The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Apr. 29, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andrew T. Forsyth, Kirkland, WA (US);

Brian J. Hickmann, Sherwood, OR (US);

Jonathan C. Hall, Hillsboro, OR (US);

Christopher J. Hughes, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 12/0875 (2016.01); G06F 12/1027 (2016.01); G06F 15/80 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3853 (2013.01); G06F 9/3017 (2013.01); G06F 9/30018 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30098 (2013.01); G06F 9/30105 (2013.01); G06F 9/30145 (2013.01); G06F 9/30163 (2013.01); G06F 9/3804 (2013.01); G06F 9/3836 (2013.01); G06F 9/3887 (2013.01); G06F 12/0875 (2013.01); G06F 12/1027 (2013.01); G06F 13/4282 (2013.01); G06F 15/8007 (2013.01); G06F 9/3824 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/452 (2013.01); G06F 2212/68 (2013.01);
Abstract

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.


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