The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2024
Filed:
Aug. 28, 2023
Intel Corporation, Santa Clara, CA (US);
Robert C. Valentine, Kiryat Tivon, IL;
Jesus Corbal San Adrian, King City, OR (US);
Roger Espasa Sans, Barcelona, ES;
Robert D. Cavin, San Francisco, CA (US);
Bret L. Toll, Hillsboro, OR (US);
Santiago Galan Duran, Molins de Rei, ES;
Jeffrey G. Wiedemeier, Austin, TX (US);
Sridhar Samudrala, Austin, TX (US);
Milind Baburao Girkar, Sunnyvale, CA (US);
Edward Thomas Grochowski, San Jose, CA (US);
Jonathan Cannon Hall, Hillsboro, OR (US);
Dennis R. Bradford, Portland, OR (US);
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
James C Abel, Phoenix, AZ (US);
Mark Charney, Lexington, MA (US);
Seth Abraham, Tempe, AZ (US);
Suleyman Sair, Phoenix, AZ (US);
Andrew Thomas Forsyth, Kirkland, WA (US);
Lisa Wu, New York, NY (US);
Charles Yount, Phoenix, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.