John H Givens

This inventor holds 48 USPTO granted patents, primarily in Semiconductor Fabrication. Top assignees: Micron Technology Incorporated, Micro Technology, Inc.. Active years: 1997-2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John H Givens. Retrieved from https://idiyas.com/inventor/john-h-givens

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 48

% Patents Active = 89.6

Average Co-Inventor Count = 1.4

ph-index = 11

Forward Citations = 409(Granted Patents)

Location History:

Boise, ID (US) (1997 - 1999)
Meridan, ID (US) (2002)
San Antonio, TX (US) (2001 - 2004)
Meridian, ID (US) (1998 - 2009)

Company Filing History:

47 out of 39,294

Micron Technology Incorporated

patents

1 out of 59

Micro Technology, Inc.

patents

Years Active: 1997-2009

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Areas of Expertise:

Metal Fill

Interconnect Structures

High Aspect Ratio

Thermal Processing

Silicon Hard Mask

Integrated Circuit

Electrical Connection

Microelectronic Devices

CMP Process

Sputtering Apparatus

Alloy

Conductive Components

48 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7510961 - Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure (2009-03-31),

2. 6984874 - Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT (2006-01-10),

3. 6812139 - Method for metal fill by treatment of mobility layers (2004-11-02),

4. 6790764 - Processing methods for providing metal-comprising materials within high aspect ratio openings (2004-09-14),

5. 6787472 - Utilization of disappearing silicon hard mask for fabrication of semiconductor structures (2004-09-07),

6. 6787447 - Semiconductor processing methods of forming integrated circuitry (2004-09-07),

7. 6784550 - Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication (2004-08-31),

8. 6781235 - Three-level unitary interconnect structure (2004-08-24),

9. 6774035 - Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication (2004-08-10),

10. 6689693 - Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures (2004-02-10),

11. 6548883 - Reduced RC between adjacent substrate wiring lines (2003-04-15),

12. 6537903 - Processing methods for providing metal-comprising materials within high aspect ratio openings (2003-03-25),

13. 6534408 - Utilization of disappearing silicon hard mask for fabrication of semiconductor structures (2003-03-18),

14. 6482735 - Method for improved metal fill by treatment of mobility layers (2002-11-19),

15. 6461963 - Utilization of disappearing silicon hard mask for fabrication of semiconductor structures (2002-10-08),

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Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]