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For the Inventor, By the Inventor

Los Altos, CA, United States of America

John C Costello

This inventor holds 27 USPTO granted patents and 1 EPO patent, primarily in Integrated Circuit Design. Top assignee: Altera Corporation. Active years: 1996-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John C Costello. Retrieved from https://idiyas.com/inventor/john-c-costello-dmsdm97r

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27

% Patents Active = 77.8

 

Average Co-Inventor Count = 3.0

ph-index = 10

Forward Citations = 704(Granted Patents)


Location History:

  • San Jose, CA (US) (1996 - 2004)
  • Los Altos, CA (US) (2004 - 2012)

Company Filing History:

goldMedal27 out of 4,333 
 
Altera Corporation
 patents

Years Active: 1996-2012

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Areas of Expertise:
Non-volatile Memory
Voltage Regulator
Electrostatic Discharge
Programmable Logic Device
I/O Noise Reduction
EEPROM Cells
High Voltage Pump
Signal Coupling
Feedback Stabilization
Impedance Matching
Margin Testing
Circuit Protection
27 patents (USPTO):Explore Patents
1. 8130538 - Non-volatile memory circuit including voltage divider with phase change memory devices (2012-03-06),
2. 7733159 - High voltage tolerance emulation using voltage clamp for oxide stress protection (2010-06-08),
3. 7639033 - On-chip voltage regulator using feedback on process/product parameters (2009-12-29),
4. RE40011 - System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly (2008-01-21),
5. 7170308 - On-chip voltage regulator using feedback on process/product parameters (2007-01-30),
6. 6836144 - Programmable series on-chip termination impedance and impedance matching (2004-12-28),
7. 6785109 - Technique for protecting integrated circuit devices against electrostatic discharge damage (2004-08-31),
8. 6781883 - Apparatus and method for margin testing single polysilicon EEPROM cells (2004-08-24),
9. 6646919 - Apparatus and method for margin testing single polysilicon EEPROM cells (2003-11-11),
10. 6369613 - Input/output drivers (2002-04-09),
11. 6366119 - Programmable logic device macrocell with improved logic capability (2002-04-02),
12. 6268623 - Apparatus and method for margin testing single polysilicon EEPROM cells (2001-07-31),
13. 6242941 - Reducing I/O noise when leaving programming mode (2001-06-05),
14. 6236260 - High voltage pump scheme incorporating an overlapping clock (2001-05-22),
15. 6184703 - Method and circuit for reducing output ground and power bounce noise (2001-02-06),

Title: John C Costello - Pioneering Inventor from Los Altos

Introduction: John C Costello is a renowned inventor based in Los Altos, California. He is known for his groundbreaking contributions to various fields through his innovative creations.

Latest Patents: John C Costello holds several patents in the areas of technology, healthcare, and consumer products. His most recent patents focus on sustainable energy solutions and advanced medical devices.

Career Highlights: With a career spanning over two decades, John C Costello has established himself as a leading figure in the world of innovation. He has worked with top companies to bring his ideas to life and has been recognized with numerous awards for his inventive spirit.

Collaborations: Throughout his career, John C Costello has collaborated with fellow inventors, researchers, and industry experts to push the boundaries of what is possible. His partnerships have led to the development of cutting-edge technologies that have had a lasting impact on society.

Conclusion: John C Costello's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a trailblazer in the world of invention. His work continues to inspire future generations of inventors to think outside the box and create solutions that shape the world we live in.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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