The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
Jan. 08, 2001
Applicant:
Inventors:
Cheng H. Huang, Cupertino, CA (US);
Chiakang Sung, Milpitas, CA (US);
John Costello, San Jose, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 ;
U.S. Cl.
CPC ...
H02H 3/22 ;
Abstract
A technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses is provided. The technique involves using a clamping device that is capable of handling both positive and negative ESD pulses to clamp each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. Without resorting to exhaustive cross-clamping, this arrangement provides a discharge path for an ESD pulse applied across any combination of power buses, ground buses, and I/O pads during an ESD event.