Sunnyvale, CA, United States of America

Jing Chyuarn Lin


Average Co-Inventor Count = 6.0

ph-index = 10

Forward Citations = 368(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (1999 - 2009)
  • Cupertino, CA (US) (2009 - 2016)

Company Filing History:


Years Active: 1999-2016

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12 patents (USPTO):

Title: Innovations of Jing Chyuarn Lin

Introduction

Jing Chyuarn Lin is a prominent inventor based in Sunnyvale, CA, known for his significant contributions to technology and design automation. With a total of 12 patents, Lin has made remarkable advancements in the field of electronic design automation.

Latest Patents

One of Lin's latest patents focuses on the placement of single-bit and multi-bit flip-flops. This technology discloses methods for replacing single-bit flip-flops with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops. Another notable patent involves improving pre-route and post-route net correlation. This method includes performing an initial placement, virtual routing, and lower-effort actual routing for design optimization. The results from virtual routing and lower-effort actual routing are compared to identify nets with miscorrelation. Based on these findings, net routing constraints and scaling factors can be assigned to enhance the design's routing efficiency.

Career Highlights

Throughout his career, Jing Chyuarn Lin has worked with leading companies in the industry, including Synopsys, Inc. and O-in Design Automation, Inc. His expertise in electronic design automation has positioned him as a key player in the field.

Collaborations

Lin has collaborated with notable professionals, including Tai An Ly and Jean-Charles Giomi, who have contributed to his innovative projects and advancements in technology.

Conclusion

Jing Chyuarn Lin's contributions to technology through his patents and collaborations highlight his role as a leading inventor in the field of electronic design automation. His work continues to influence advancements in technology and design efficiency.

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