The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2001
Filed:
Oct. 20, 1997
Chian-Min Richard Ho, Mountain View, CA (US);
Robert Kristianto Mardjuki, Danville, CA (US);
David Lansing Dill, Redwood City, CA (US);
Jing Chyuarn Lin, Sunnyvale, CA (US);
Ping Fai Yeung, San Jose, CA (US);
Paul II Estrada, Los Alto, CA (US);
Jean-Charles Giomi, Menlo Park, CA (US);
Tai An Ly, Fremont, CA (US);
Kalyana C. Mulam, San Jose, CA (US);
Lawrence Curtis Widdoes, Jr., San Jose, CA (US);
Paul Andrew Wilcox, Palo Alto, CA (US);
O-In Design Automation, San Jose, CA (US);
Abstract
A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.