Jens Polney

This inventor holds 7 USPTO granted patents and 1 published patent application. Top assignees: Micron Technology Incorporated, Qimonda Ag. Active years: 2009-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jens Polney. Retrieved from https://idiyas.com/inventor/jens-polney-mssgm5w4

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 7 (Patent Applications = 1)

% Patents Active = 71.4

Average Co-Inventor Count = 1.7

ph-index = 2

Forward Citations = 18(Granted Patents)

Location History:

Munich, DE (2009)
Feldkirchen, DE (2017 - 2021)

Company Filing History:

5 out of 39,253

Micron Technology Incorporated

Years Active: 2009-2026

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7 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12736999 - Systems and techniques for clock doubling (2026-09-15),

2. 12628690 - Layouts of data pads on a semiconductor die (2026-05-12),

3. 10943627 - Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device (2021-03-09),

4. 10297298 - Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device (2019-05-21),

5. 9818462 - Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device (2017-11-14),

6. 7573760 - Integrated circuit for sampling a sequence of data packets at a data output (2009-08-11),

7. 7554875 - Bus structure, memory chip and integrated circuit (2009-06-30),

Title: Jens Polney: Innovator in Integrated Circuit Technology

Introduction

Jens Polney is a notable inventor based in Munich, Germany. He has made significant contributions to the field of integrated circuits, holding a total of 7 patents. His work focuses on enhancing data processing and transmission technologies.

Latest Patents

Jens Polney's latest patents include an integrated circuit for sampling a sequence of data packets at a data output. This innovative circuit features a sampling circuit that operates based on sampling edges, responding to data packets generated by a sequence of request commands. The control section of the circuit is designed to produce these sampling edges, utilizing multiple transmission branches that each contain a copy of the operating section. Additionally, he has developed a bus structure that comprises several driver circuits, which are capable of providing output signals upon receiving input signals. This bus structure is designed to optimize the connection order among the driver circuits, enhancing the efficiency of data transmission.

Career Highlights

Jens Polney is currently employed at Qimonda AG, where he continues to push the boundaries of integrated circuit technology. His work has been instrumental in advancing the capabilities of data processing systems.

Collaborations

Throughout his career, Jens has collaborated with notable colleagues, including Christian Sichert and Rainer Bartenschlager. These partnerships have contributed to the development of innovative solutions in the field of electronics.

Conclusion

Jens Polney's contributions to integrated circuit technology exemplify his commitment to innovation and excellence. His patents reflect a deep understanding of data processing and transmission, positioning him as a key figure in the industry.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: