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For the Inventor, By the Inventor

Kaohsiung, Taiwan

Jeng-Shiou Chen

USPTO Granted Patents = 22

Average Co-Inventor Count = 3.2

ph-index = 4

Forward Citations = 33(Granted Patents)


Location History:

  • Hsinchu, TW (2021)
  • Kaohsiung, TW (2015 - 2024)

Company Filing History:

goldMedal22 out of 40,635 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2015-2024

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22 patents (USPTO):Explore Patents
1. 11961761 - Mitigating pattern collapse (2024-04-16),
2. 11682580 - Interconnect structure and method of forming the same (2023-06-20),
3. 11088021 - Interconnect structure and method of forming the same (2021-08-10),
4. 11043453 - Method of preventing pattern collapse (2021-06-22),
5. 10985054 - Interconnect structure and method of forming the same (2021-04-20),
6. 10950495 - Mitigating pattern collapse (2021-03-16),
7. 10714383 - Interconnect structure and method of forming the same (2020-07-14),
8. 10679895 - Interconnect structure and method of forming the same (2020-06-09),
9. 10515895 - Method of preventing pattern collapse (2019-12-24),
10. 10290538 - Interconnect structure and method of forming the same (2019-05-14),
11. 10115630 - Interconnect structure and method of forming the same (2018-10-30),
12. 10043706 - Mitigating pattern collapse (2018-08-07),
13. 9892960 - Interconnect structure and method of forming the same (2018-02-13),
14. 9502287 - Method of preventing pattern collapse (2016-11-22),
15. 9412650 - Interconnect structure and method of forming the same (2016-08-09),

Title: Innovations by Jeng-Shiou Chen: A Leader in Semiconductor Technology

Introduction: Jeng-Shiou Chen, based in Kaohsiung, Taiwan, is a renowned inventor with a remarkable portfolio that includes 22 patents. His contributions to the field of semiconductor technology reflect not only his creativity but also his commitment to advancing industry standards.

Latest Patents: Among his latest innovations are two notable patents focused on mitigating pattern collapse. The first patent introduces techniques and systems designed to alleviate pattern collapse in semiconductor structures. It describes a semiconductor configuration featuring an extreme low-k dielectric region that is integral to the function of vias or metal lines. The innovative approach utilizes different stages of patterning for various metal line portions, thus effectively addressing the challenges posed by pattern collapse.

The second patent details an interconnect structure along with a methodology for its formation. It includes a lower etch stop layer, followed by a low-k dielectric layer, and an upper conductive feature that operates through a supporting layer. This design ensures not only structural integrity but also enhances performance by addressing gaps along interfaces within the interconnect structure.

Career Highlights: Jeng-Shiou Chen's work is primarily rooted in his role at Taiwan Semiconductor Manufacturing Company Ltd. His expertise has significantly propelled advancements in semiconductor design and manufacturing processes. Over the years, his innovative solutions have positioned him as an essential figure in the development of next-generation semiconductor technologies.

Collaborations: Chen has collaborated with notable colleagues, including Chih-Yuan Ting and Jyu-Horng Shieh. These partnerships have fostered a collaborative environment that encourages innovation and effective problem-solving across various projects within the semiconductor industry.

Conclusion: Jeng-Shiou Chen exemplifies the spirit of innovation in the semiconductor field. His extensive patent portfolio and collaborative efforts underline his influential role in shaping modern technology. As he continues to innovate, the impact of his work will undoubtedly resonate within the industry for years to come.

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