The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Mar. 15, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Chih-Yuan Ting, Taipei, TW;

Ya-Lien Lee, Baoshan Township, TW;

Chung-Wen Wu, Zhubei, TW;

Jeng-Shiou Chen, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76838 (2013.01); H01L 21/76844 (2013.01); H01L 21/76867 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.


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