Fort Collins, CO, United States of America

Jeffrey Scott Brown

This inventor holds 29 USPTO granted patents and 1 published patent application and 2 EPO patents, primarily in Memory Optimization. Top assignees: Lsi Corporation, Lsi Logic Corporation, Avago Technologies General IP (Singapore) Pte. Ltd.. Active years: 2001-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeffrey Scott Brown. Retrieved from https://idiyas.com/inventor/jeffrey-scott-brown-34d5sgyk

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 29 

% Patents Active = 44.8

 

Average Co-Inventor Count = 1.5

ph-index = 6

Forward Citations = 225(Granted Patents)


Location History:

  • Ft. Collins, CO (US) (2007)
  • Fort Collins, CO (US) (2001 - 2014)
  • Fort Colllins, CO (US) (2015)

Company Filing History:


Years Active: 2001-2015

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Areas of Expertise:
Signal Integrity
Power Optimization
Integrated Circuit
Memory Access
Clock Skew
Power Supply Monitoring
Tristate Bus Keeper
Soft Error Rate
ROM Architecture
Timing Analysis
Memory Inversion
Asynchronous Memory
29 patents (USPTO):Explore Patents

Title: Innovations and Contributions of Jeffrey Scott Brown

Introduction

Jeffrey Scott Brown, based in Fort Collins, CO, has made significant strides in the field of technology with a remarkable portfolio of 29 patents. His work primarily focuses on enhancing signal integrity in electronic interfaces and optimizing circuit performance, showcasing his expertise and innovative spirit in the engineering domain.

Latest Patents

One of his latest patents, titled "Parallel interface pattern modification for addressing signal integrity concerns," introduces a method for improving signal integrity between source and destination devices. This involves analyzing data patterns to identify potential coupling noise and simultaneous switching output (SSO) effects, generating modified data patterns to mitigate these issues, and transmitting both the modified pattern and the modification details to the destination device.

Another notable patent, "Optimization of library slew ratio based circuit," provides a technique for minimizing sequential overhead in flip-flop circuits. This patent emphasizes equalizing setup times and delays in clock to Q transitions, ensuring that large setup times are not necessary. By employing optimization techniques, both rising and falling data transitions can be handled efficiently.

Career Highlights

Throughout his career, Jeffrey Scott Brown has been associated with prestigious companies, including LSI Corporation and LSI Logic Corporation. His work in these organizations has contributed to advancements in digital circuit design and signal processing.

Collaborations

During his journey, Jeffrey has had the opportunity to collaborate with esteemed professionals such as Mark Franklin Turner and Jonathan W Byrn. These collaborations have undoubtedly enriched his experience and led to innovative outcomes in various technology projects.

Conclusion

Jeffrey Scott Brown's contributions to the field through his patents reveal a commitment to innovation and improvement in electronic design. His work continues to influence the industry, ensuring that technology evolves to meet the demands of modern applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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