Transistor bit cell rom architecture

Abstract

An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line. The bit cell is programmed during the ROM generation by connecting the drain of either the PMOS (logic level 1) or the NMOS (logic level 0) to the bit line.