The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2013
Filed:
Nov. 02, 2010
Jeffrey S. Brown, Fort Collins, CO (US);
Mark Franklin Turner, Longmont, CO (US);
Jeffrey S. Brown, Fort Collins, CO (US);
Mark Franklin Turner, Longmont, CO (US);
LSI Corporation, San Jose, CA (US);
Abstract
An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.