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For the Inventor, By the Inventor

Tracy, CA, United States of America

Jeffrey D Chamberlain

This inventor holds 26 USPTO granted patents and 6 published patent applications and 2 EPO patents, primarily in Cache Memory Optimization. Top assignee: Intel Corporation. Active years: 2005-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeffrey D Chamberlain. Retrieved from https://idiyas.com/inventor/jeffrey-d-chamberlain

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 69.2

 

Average Co-Inventor Count = 5.9

ph-index = 4

Forward Citations = 76(Granted Patents)


Location History:

  • Dublin, CA (US) (2021)
  • Tracy, CA (US) (2005 - 2024)

Company Filing History:

goldMedal26 out of 56,322 
 
Intel Corporation
 patents

Years Active: 2005-2025

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Areas of Expertise:
Cache Memory
Multi-Processor
Resource Bandwidth
Interconnect Routing
Latency Reduction
FaaS Enhancements
Processor Design
Coherent Interconnect
Caching Agent
Memory Transaction
Quality of Service
Power Savings
26 patents (USPTO):Explore Patents
1. 12198186 - Systems, apparatuses, and methods for resource bandwidth enforcement (2025-01-14),
2. 12066939 - Cache line demote infrastructure for multi-processor pipelines (2024-08-20),
3. 11966330 - Link affinitization to reduce transfer latency (2024-04-23),
4. 11922220 - Function as a service (FaaS) system enhancements (2024-03-05),
5. 11899615 - Multiple dies hardware processors and methods (2024-02-13),
6. 11586579 - Multiple dies hardware processors and methods (2023-02-21),
7. 11294852 - Multiple dies hardware processors and methods (2022-04-05),
8. 11256657 - System, apparatus and method for adaptive interconnect routing (2022-02-22),
9. 10936490 - System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms (2021-03-02),
10. 10795853 - Multiple dies hardware processors and methods (2020-10-06),
11. 10705961 - Scalably mechanism to implement an instruction that monitors for writes to an address (2020-07-07),
12. 10339060 - Optimized caching agent with integrated directory cache (2019-07-02),
13. 10338974 - Virtual retry queue (2019-07-02),
14. 10204049 - Value of forward state by increasing local caching agent forwarding (2019-02-12),
15. 10140213 - Two level memory full line writes (2018-11-27),

Title: The Inventor Jeffrey D Chamberlain: Pioneering Innovations in Tracy, CA

Introduction: Jeffrey D Chamberlain is a distinguished inventor based in Tracy, CA, known for his groundbreaking contributions to various fields through his innovative creations.

Latest Patents: Jeffrey D Chamberlain holds several patents in the areas of renewable energy technologies, sustainable agriculture solutions, and advanced medical devices, showcasing his versatility and ingenuity.

Career Highlights: With a career spanning over two decades, Jeffrey D Chamberlain has established himself as a visionary inventor, with a keen focus on developing solutions that address pressing global challenges.

Collaborations: Throughout his career, Jeffrey D Chamberlain has collaborated with leading research institutions, universities, and companies to bring his inventions to life, fostering a culture of innovation and progress.

Conclusion: Jeffrey D Chamberlain's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors, leaving an indelible mark on the world of technology and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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