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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10705961 B1

PDFFull Text
Date of Patent:
Jul. 07, 2020

Filed:

Sep. 27, 2013

Scalably mechanism to implement an instruction that monitors for writes to an address

Applicants:

Yen-cheng Liu, Portland, OR (US);

Bahaa Fahim, San Jose, CA (US);

Erik G. Hallnor, Beaverton, OR (US);

Jeffrey D. Chamberlain, Tracy, CA (US);

Stephen R. Van Doren, Portland, OR (US);

Antonio Juan, Barcelona, ES;

Inventors:

Yen-Cheng Liu, Portland, OR (US);

Bahaa Fahim, San Jose, CA (US);

Erik G. Hallnor, Beaverton, OR (US);

Jeffrey D. Chamberlain, Tracy, CA (US);

Stephen R. Van Doren, Portland, OR (US);

Antonio Juan, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Nicholson De Vos Webster & Elliott LLP

Primary Examiner:

William B Partridge

Assistant Examiner:

Eric T Loonan

Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/084 (2016.01); G06F 12/0831 (2016.01); G06F 12/0846 (2016.01); G06F 12/0811 (2016.01); G06F 9/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 9/00 (2013.01); G06F 12/0811 (2013.01); G06F 12/0833 (2013.01); G06F 12/0846 (2013.01); G06F 2212/1016 (2013.01);
Abstract

A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

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