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For the Inventor, By the Inventor

Essex Junction, VT, United States of America

Jeanne P Bickford

This inventor holds 73 USPTO granted patents and 4 published patent applications, primarily in Integrated Circuit Design (CPC class G06F). Top assignees: International Business Machines Corporation, Globalfoundries Inc., Mentor Graphics Corporation. Active years: 2006-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeanne P Bickford. Retrieved from https://idiyas.com/inventor/jeanne-p-bickford

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 73 

% Patents Active = 32.9

Average Co-Inventor Count = 4.2

ph-index = 8

Forward Citations = 238(Granted Patents)

Forward Citations (Not Self Cited) = 183(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Essex Juntion, VT (US) (2015)
  • Essex Junction, VT (US) (2006 - 2020)

Company Filing History:

goldMedal49 out of 166,351 
 
International Business Machines Corporation
 patents
silverMedal21 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal2 out of 672 
 
Mentor Graphics Corporation
 patents
4. 1 out of 59 
 
Globalfoundries U.S. 2 LLC
 patents

Years Active: 2006-2020

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Areas of Expertise:
Integrated Circuit
Voltage Binning
Reliability Qualification
Performance Optimization
Temperature Management
Electromigration
Power Control
Manufacturing Qualification
Path Delay Analysis
Chip Design
Yield Optimization
Semiconductor Device
73 patents (USPTO):Explore Patents
1. 10794952 - Product performance test binning (2020-10-06),
2. 10539611 - Integrated circuit chip reliability qualification using a sample-specific expected fail rate (2020-01-21),
3. 10295592 - Pre-test power-optimized bin reassignment following selective voltage binning (2019-05-21),
4. 10067184 - Product performance test binning (2018-09-04),
5. 10013519 - Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation (2018-07-03),
6. 9940430 - Burn-in power performance optimization (2018-04-10),
7. 9891275 - Integrated circuit chip reliability qualification using a sample-specific expected fail rate (2018-02-13),
8. 9865486 - Timing/power risk optimized selective voltage binning using non-linear voltage slope (2018-01-09),
9. 9852259 - Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks (2017-12-26),
10. 9791502 - On-chip usable life depletion meter and associated method (2017-10-17),
11. 9772374 - Selective voltage binning leakage screen (2017-09-26),
12. 9767240 - Temperature-aware integrated circuit design methods and systems (2017-09-19),
13. 9759767 - Pre-test power-optimized bin reassignment following selective voltage binning (2017-09-12),
14. 9740815 - Electromigration-aware integrated circuit design methods and systems (2017-08-22),
15. 9653330 - Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning (2017-05-16),

Title: Jeanne P. Bickford: Innovator in Integrated Circuit Reliability

Introduction

Jeanne P. Bickford is a distinguished inventor based in Essex Junction, Vermont, known for her extensive contributions to the field of integrated circuits. With an impressive portfolio of 73 patents, Bickford has made significant advancements in the reliability and performance testing of integrated circuit chips.

Latest Patents

Among her latest innovations is the "Product performance test binning," which focuses on a method and system for significantly enhancing the testing process of integrated circuits. This method includes several steps to optimize the testing of pathways within an integrated circuit chip, ensuring reliable performance under varied electrical conditions. This method first selects a voltage bin with specified frequency ranges and conducts a functional path test on designated data paths. If a pathway fails, the testing voltage is adjusted, and the process repeats until all paths are validated.

Another notable patent from Bickford is the "Integrated circuit chip reliability qualification using a sample-specific expected fail rate." This method revolutionizes how integrated circuit chips are stress-tested and qualified. Instead of using a general overall fail rate, Bickford’s approach calculates a unique expected fail rate for specific samples based on the manufacturing process, contributing to better reliability assessments for IC chips.

Career Highlights

Throughout her career, Bickford has worked with well-respected companies in the technology sector, including International Business Machines Corporation (IBM) and GlobalFoundries Inc. Her experience in these globally recognized organizations has provided her with a platform to innovate and contribute to the development of state-of-the-art integrated circuit technologies.

Collaborations

In her professional journey, Bickford has had the opportunity to work alongside talented individuals such as Nazmul Habib and Susan K. Lichtensteiger. These collaborations have allowed her to expand her expertise and contribute to pivotal projects in integrated circuit development.

Conclusion

Jeanne P. Bickford's commitment to innovation in integrated circuit reliability and performance testing is evident through her impressive patent count and the groundbreaking methods she has developed. As a leading inventor, her work continues to influence the field and pave the way for advancements in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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