The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2019
Filed:
Jun. 13, 2017
Globalfoundries Inc., Grand Cayman, KY;
Igor Arsovski, Williston, VT (US);
Jeanne P. Bickford, Essex Junction, VT (US);
Paul J. Grzymkowski, Essex Junction, VT (US);
Susan K. Lichtensteiger, Essex Junction, VT (US);
Robert J. McMahon, Essex Junction, VT (US);
Troy J. Perry, Georgia, VT (US);
David M. Picozzi, Ferrisburgh, VT (US);
Thomas G. Sopchak, Williston, VT (US);
GLOBAL FOUNDRIES INC., Grand Cayman, KY;
Abstract
Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.