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Wellington, CO, United States of America

Jayen J Desai

USPTO Granted Patents = 11

Average Co-Inventor Count = 2.5

ph-index = 4

Forward Citations = 40(Granted Patents)

Location History:

Fort Collins, CO (US) (2002 - 2003)
Wellington, CO (US) (2007 - 2017)

Company Filing History:

6 out of 27,412

Hewlett-packard Development Company, L.P.

4 out of 54,750

Intel Corporation

Hewlett-packard Company

Years Active: 2002-2025

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11 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12500583 - Clock interpolation system for eye-centering (2025-12-16),

2. 9628092 - Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning (2017-04-18),

3. 9178502 - Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning (2015-11-03),

4. 9124257 - Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement (2015-09-01),

5. 7873132 - Clock recovery (2011-01-18),

6. 7610526 - On-chip circuitry for bus validation (2009-10-27),

7. 7498858 - Interpolator systems with linearity adjustments and related methods (2009-03-03),

8. 7391221 - On-die impedance calibration (2008-06-24),

9. 7276952 - Clock signal generation using digital frequency synthesizer (2007-10-02),

10. 6583650 - Latching annihilation based logic gate (2003-06-24),

11. 6459304 - Latching annihilation based logic gate (2002-10-01),

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