The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Aug. 17, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jayen Desai, Wellington, CO (US);

Gerald Pasdast, San Jose, CA (US);

Peipei Wang, San Jose, CA (US);

Debendra Das Sharma, Saratoga, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/13 (2014.01); G06F 1/12 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/13 (2013.01); G06F 1/12 (2013.01); H03K 2005/00013 (2013.01);
Abstract

Embodiments herein relate to a clock interpolation system. The system may be configured to identify, at a change in logical state of a recovered clock signal, a logical state of a first signal when the first signal is delayed by a delay value. The system may be further configured to identify, at a change in logical state of a second signal, a logical state of the clock signal when the clock signal is delayed by the delay value. Based on the two identifications, the delay value and/or a timing of the clock signal may be adjusted. Other embodiments may be described and/or claimed.


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