The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Dec. 27, 2013
Applicants:

Erin D. Francom, Fort Collins, CO (US);

Jayen J. Desai, Wellington, CO (US);

Matthew R. Peters, Fort Collins, CO (US);

Nicholas J. Denler, Beaverton, OR (US);

Inventors:

Erin D. Francom, Fort Collins, CO (US);

Jayen J. Desai, Wellington, CO (US);

Matthew R. Peters, Fort Collins, CO (US);

Nicholas J. Denler, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/16 (2006.01); H03K 5/13 (2014.01); H03K 5/14 (2014.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); H03L 7/08 (2013.01);
Abstract

A delay line has at least four delay stages coupled together in a series, two multiplexers, and a phase interpolator. The first multiplexer has a first input coupled to an output of the first delay stage, and a second input coupled to an output of the third delay stage. Similarly, the second multiplexer has a first input coupled to an output of the second delay stage, and a second input coupled to an output of the fourth delay stage. The phase interpolator is coupled to outputs of the first and second multiplexers, and has an output.


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