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For the Inventor, By the Inventor

Williston, VT, United States of America

Jay Gerald Heaslip

USPTO Granted Patents = 14

Average Co-Inventor Count = 2.5

ph-index = 4

Forward Citations = 94(Granted Patents)


Location History:

  • Chittenden County, VT (US) (1997)
  • Willifton, VT (US) (2003)
  • Williston, VT (US) (1992 - 2022)

Company Filing History:

goldMedal14 out of 164,108 
 
International Business Machines Corporation
 patents

Years Active: 1992-2022

where 'Filed Patents' based on already Granted Patents

14 patents (USPTO):
1. 11221957 - Promotion of ERAT cache entries (2022-01-11),
2. 10884943 - Speculative checkin of ERAT cache entries (2021-01-05),
3. 10599569 - Maintaining consistency between address translations in a data processing system (2020-03-24),
4. 9740629 - Tracking memory accesses when invalidating effective address to real address translations (2017-08-22),
5. 9727483 - Tracking memory accesses when invalidating effective address to real address translations (2017-08-08),
6. 9286129 - Termination of requests in a distributed coprocessor system (2016-03-15),
7. 8918558 - Round robin priority selector (2014-12-23),
8. 7106110 - Clock dithering system and method during frequency scaling (2006-09-12),
9. 6643807 - Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test (2003-11-04),
10. 6560695 - Dynamic pipe staging adder (2003-05-06),
11. 5930832 - Apparatus to guarantee TLB inclusion for store operations (1999-07-27),
12. 5768556 - Method and apparatus for identifying dependencies within a register (1998-06-16),
13. 5634026 - Source identifier for result forwarding (1997-05-27),
14. 5101372 - Optimum performance standard cell array multiplier (1992-03-31),

Title: The Innovations of Jay Gerald Heaslip

Introduction

Jay Gerald Heaslip is a notable inventor based in Williston, Vermont, with a remarkable portfolio of 14 patents. His work primarily focuses on advancements in computer processing and memory management systems. Heaslip's contributions have significantly impacted the field of technology, particularly in the realm of effective address translation.

Latest Patents

Among his latest patents, Heaslip has developed methods for the promotion of Effective Address to Real Address Translation (ERAT) cache entries. This innovation involves processing information in a processor by receiving requests for ERAT, determining permissions misses, and adjusting permissions accordingly. Additionally, he has introduced a method for the speculative check-in of ERAT cache entries, which includes setting thresholds for free cache entries and allocating active entries to be checked into a memory management unit (MMU).

Career Highlights

Heaslip has built a successful career at the International Business Machines Corporation (IBM), where he has been instrumental in developing cutting-edge technologies. His expertise in computer systems and memory management has led to significant advancements in the efficiency and performance of processing systems.

Collaborations

Heaslip has collaborated with several talented individuals in his field, including Bartholomew Blaner and Robert Dov Herzl. These partnerships have fostered innovation and contributed to the successful development of his patented technologies.

Conclusion

Jay Gerald Heaslip's contributions to the field of computer processing and memory management are noteworthy. His innovative patents and collaborations reflect his commitment to advancing technology. He continues to be a significant figure in the realm of inventions and innovations.

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