The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 1998
Filed:
Dec. 22, 1995
Miles Gaylord Canada, Colchester, VT (US);
Walter Esling, Colorado Springs, CO (US);
Jay Gerald Heaslip, Williston, VT (US);
Stephen William Mahin, Underhill, VT (US);
Pamela A Wilcox, Burlington, VT (US);
James Hesson, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchical arrangement of register storage sets. In its preferred embodiment, the apparatus comprises a storage means for storing a bit map, which bit map is configured to provide bit map identifications identifying designated register storage sets. The bit map represents the hierarchical arrangement. The apparatus further comprises a logic means for logically treating information, which logic means is coupled with the storage means and with the computer system. The logic means receives a first bit map identification from a first instruction (the first bit map identification identifies a first register storage set), and receives a second bit map identification from a second instruction (the second bit map identification identifies a second register storage set. The second instruction is subsequent in the succession to the first instruction. The first register storage set is a first storage locus for storing a target operand of the first instruction; the second register storage set is a second storage locus for storing a source operand for the second instruction. The logical treating effects the identifying of dependencies between the target operand and the source operand.