International Business Machines Corporation

Jay Gerald Heaslip

Bartholomew Blaner

Robert Dov Herzl

Jeffrey A Stuecheli

Jody B Joyner

Kenneth Anthony Lauricella

Miles G Canada

Cedric Lichtenau

Brian Mitchell Bass

Thomas Pflueger

Charles David Wait

Gerard M Salem

Jon K Kriegel

Benjamin Herrenschmidt

Gary William Maier

Ross Boyd Leavens

Arnold S Tran

Stephen William Mahin

James Henry Hesson

Erwin B Cohen

Mathew I Ringler

Timothy J Von Reyn

Walter Esling

Pamela A Wilcox

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

Promotion of ERAT cache entries

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.

Speculative checkin of ERAT cache entries

A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests are indicated for an accelerator unit (AU). In response to detecting that the invalidation requests are indicated, the MMU issues a raise barrier request for the AU. In response to detecting a raise barrier response from the AU to the raise barrier request the MMU issues the invalidation requests to the AU. In response to detecting an address translation invalidation response from the AU to each of the invalidation requests, the MMU issues a lower barrier request to the AU. In response to detecting a lower barrier response from the AU to the lower barrier request, the MMU resumes handling address translation check-in and check-out requests received from the AU.

Maintaining consistency between address translations in a data processing system

According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Tracking memory accesses when invalidating effective address to real address translations

A system and method of terminating processing requests dispatched to a coprocessor hardware accelerator in a multi-processor computer system based on matching various fields in the request made to the coprocessor to identify the process to be terminated. A kill command is initiated by a write operation to a coprocessor block kill register and has match enable and value for each field in the coprocessor request to be terminated. Enabled fields may have one or more values associated with a single request or multiple requests for the same coprocessor. At least one match enable must be set to initiate a kill request. A process kill active signal prevents other coprocessor jobs from moving between operational stages in the coprocessor hardware accelerator. Processing jobs that are idle or do not match the fields with match enables set signal done with no match and continue processing. Processing jobs that do match the fields with match enables set are terminated and signal done with match. When all processing jobs have signaled done, a done bit is set in the coprocessor block kill register to indicate completion of the kill to the initiating software. The register also holds the match status of each processing job.

Termination of requests in a distributed coprocessor system

Method and structures for performing round robin priority selection receive an input vector into an input port. The methods and structures group the bits of the input vector into groups of bits and supply the groups of bits to round robin priority selectors. Then, the methods and structures simultaneously identify an individual group priority bit within each group of bits based on the starting bit location, using the round robin priority selectors. The methods and structures also choose, using the group selector, a round robin priority selector based on the starting bit location. The methods and structures then output, from the group selector to a multiplexor, the individual group priority bit of the selected round robin priority selector. Following this the method outputs, from the multiplexor, an output vector having a first value (e.g., 1) only in the individual group priority bit output by the group selector.

Round robin priority selector

A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.

Clock dithering system and method during frequency scaling

A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.

Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test

The present invention provides a method and apparatus for processing instructions in which the time allowed for the execution of an instruction is dynamically allocated. The allocation of time for execution of instruction occurs after the instruction is sent to the execution unit. The execution unit determines whether it can complete the instruction during the current processor cycle. In response to an ability to complete the instruction within the current processor cycle, the execution unit issues a busy signal to the reservation station. The reservation station continues to hold the next instruction until the execution until is capable of processing it.

Dynamic pipe staging adder

A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit includes means for detecting when a translation has been evicted from a lookaside buffer and means for communicating eviction information to the means for retiring instructions in program order. The means for retiring instructions in program order includes means for holding a storage related instruction which causes a miss in the lookaside buffer or in the cache in a first pass of execution until the instruction becomes the oldest storage related instruction in program sequence and further includes means responsive to the eviction information for flushing all storage related instructions except the current storage related instruction. The system avoids the occurrence of misses in the buffer late in execution (e.g., PASS 2 or later), thus avoiding a necessity for complex recovery provisions.

Apparatus to guarantee TLB inclusion for store operations

An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchical arrangement of register storage sets. In its preferred embodiment, the apparatus comprises a storage means for storing a bit map, which bit map is configured to provide bit map identifications identifying designated register storage sets. The bit map represents the hierarchical arrangement. The apparatus further comprises a logic means for logically treating information, which logic means is coupled with the storage means and with the computer system. The logic means receives a first bit map identification from a first instruction (the first bit map identification identifies a first register storage set), and receives a second bit map identification from a second instruction (the second bit map identification identifies a second register storage set. The second instruction is subsequent in the succession to the first instruction. The first register storage set is a first storage locus for storing a target operand of the first instruction; the second register storage set is a second storage locus for storing a source operand for the second instruction. The logical treating effects the identifying of dependencies between the target operand and the source operand.

Method and apparatus for identifying dependencies within a register

In a method and apparatus for result forwarding, a source operand compare circuit for a reservation station for a superscalar processor having a plurality of execution units, includes a source identifier for identifying an execution unit that will produce a needed result. The source identifier is included with a rename tag associated with a respective source operand. A multiplexor controlled by the source identifier directs the result of an execution unit to a comparator. The comparator compares the rename tag with a specific reservation station identity. As a result of this comparison, the needed data result is supplied to the respective source operand.

Source identifier for result forwarding

A cell array multiplier uses unique adder interconnections to increase the multiplier output speed. More specifically, adder connections for each column of the multiplier are generated by maintaining a list of available inputs for each column. Three inputs are assigned to each full adder, wherein the inputs are chosen from the list based upon the time delay before the input is available. Once three inputs are chosen and assigned to an adder, these inputs are delected from the list and the sum of the newly assigned adder is added to the list. This process is repeated until only a sum remains on the list, which represents the output of that column. By using this method, each stage of each column is assigned the earliest available inputs possible for the column and stage in question. The present invention uses estimates of the time delays of the sum and carry for each full adder. To generate the most efficient configuration, accurate sum and carry delay estimates are necessary.

Growing community of inventors

Williston, VT, United States of America

Jay Gerald Heaslip