Saratoga, CA, United States of America

Jason Zse-cherng Lin

This inventor holds 6 USPTO granted patents and 2 published patent applications. Top assignees: Dmo Systems Limited, Applied Materials, Inc.. Active years: 2015-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jason Zse-cherng Lin. Retrieved from https://idiyas.com/inventor/jason-zse-cherng-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6 

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 2

Forward Citations = 11(Granted Patents)


Company Filing History:


Years Active: 2015-2021

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6 patents (USPTO):Explore Patents

Title: Jason Zse-cherng Lin: Innovator in Semiconductor Technology

Introduction

Jason Zse-cherng Lin is a prominent inventor based in Saratoga, CA (US). He has made significant contributions to the field of semiconductor technology, holding a total of 6 patents. His innovative methodologies have advanced the processes involved in semiconductor device fabrication and defect screening.

Latest Patents

One of his latest patents is titled "Methodology of incorporating wafer physical measurement with digital simulation for improving semiconductor device fabrication." This patent introduces a hot spot methodology that integrates wafer physical measurements with digital simulations to identify and monitor critical hot spots. The process involves collecting physical data from processed wafers at various target locations. Digital simulations generate hot spot candidates and corresponding data based on optical proximity and lithographic process correction models. Data analytics plays a crucial role in correlating the collected wafer data with simulation data, allowing for better predictions of critical hot spots.

Another notable patent is "Auto defect screening using adaptive machine learning in semiconductor device manufacturing flow." This invention features a system for automatic defect screening that utilizes adaptive machine learning. It includes an adaptive model controller, a defect/nuisance library, and a module for executing data modeling analytics. The adaptive model controller processes defect candidates from wafer inspections and selects data samples for validation through scanning electron microscope (SEM) results. This system aims to generate and validate updated defect screening models based on model training and validation data.

Career Highlights

Throughout his career, Jason has worked with notable companies such as DMO Systems Limited and Applied Materials, Inc. His experience in these organizations has contributed to his expertise in semiconductor technology and innovation.

Collaborations

Jason has collaborated with various professionals in the field, including his coworker Shauh-Teh Juang. These collaborations have further enhanced his work and contributions to semiconductor advancements.

Conclusion

Jason Zse-cherng Lin is a distinguished inventor whose work in semiconductor technology has led to significant advancements in the industry. His innovative patents and career achievements reflect his dedication to improving semiconductor device fabrication and defect screening processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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