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For the Inventor, By the Inventor

Yokohama, Japan

Hiroshi Naruse

This inventor holds 17 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1992-2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroshi Naruse. Retrieved from https://idiyas.com/inventor/hiroshi-naruse

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 17

% Patents Active = 88.2

Average Co-Inventor Count = 3.2

ph-index = 10

Forward Citations = 371(Granted Patents)


Location History:

  • Kawasaki, JP (1994 - 1995)
  • Kanagawa-ken, JP (1999)
  • Yokohama, JP (1992 - 2007)

Company Filing History:

goldMedal17 out of 53,262 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 1992-2007

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17 patents (USPTO):Explore Patents
1. 7224003 - Solid-state image pickup apparatus (2007-05-29),
2. 7042061 - Solid-state image pickup apparatus (2006-05-09),
3. 6690423 - Solid-state image pickup apparatus (2004-02-10),
4. 6551882 - Semiconductor device manufacturing method permitting suppression of leak current through the PN junction (2003-04-22),
5. 6339237 - Semiconductor device having a memory cell region and peripheral circuit region and method of manufacturing the same (2002-01-15),
6. 5963822 - Method of forming selective epitaxial film (1999-10-05),
7. 5926725 - Method of manufacturing semiconductor devices with a reverse tapered (1999-07-20),
8. 5877540 - Epitaxial-base bipolar transistor (1999-03-02),
9. 5864180 - Semiconductor device and method for manufacturing the same (1999-01-26),
10. 5733810 - Method of manufacturing MOS type semiconductor device of vertical (1998-03-31),
11. 5665616 - Process of manufacturing a semiconductor device (1997-09-09),
12. 5614425 - Method of fabricating a bipolar transistor operable at high speed (1997-03-25),
13. 5476813 - Method of manufacturing a bonded semiconductor substrate and a (1995-12-19),
14. 5399511 - Method of manufacturing a hetero bipolar transistor (1995-03-21),
15. 5365090 - Hetero bipolar transistor and method of manufacturing the same (1994-11-15),

Title: Hiroshi Naruse: Innovator in Solid-State Image Pickup Technology

Introduction

Hiroshi Naruse is a prominent inventor based in Yokohama, Japan. He has made significant contributions to the field of solid-state image pickup technology, holding a total of 17 patents. His work has advanced the capabilities of image sensors, making them more efficient and effective.

Latest Patents

One of Naruse's latest patents is a solid-state image pickup apparatus. This invention provides a mechanism that allows for the easy discharge of signal charges in a signal accumulating section. It addresses issues such as reduction in dynamic range, thermal noise in dark states, and image lag, even when the pixel size is reduced. The apparatus incorporates a p-type silicon substrate with a pdiffusion layer for photoelectric conversion and a drain of a reading MOS field effect transistor. The design ensures that the signal accumulating section, formed by an n-type diffusion layer, operates effectively beneath the pdiffusion layer.

Career Highlights

Hiroshi Naruse has had a distinguished career at Kabushiki Kaisha Toshiba, where he has been instrumental in developing innovative technologies. His expertise in solid-state devices has positioned him as a key figure in the advancement of imaging technologies.

Collaborations

Throughout his career, Naruse has collaborated with notable colleagues, including Akiko Nomachi and Shin-ichi Taka. These partnerships have fostered a creative environment that has led to groundbreaking advancements in their field.

Conclusion

Hiroshi Naruse's contributions to solid-state image pickup technology have had a lasting impact on the industry. His innovative patents and collaborative efforts continue to shape the future of imaging technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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