Kabushiki Kaisha Toshiba

Hiroshi Naruse

Akiko Nomachi

Hiroyuki Sugaya

Shin-ichi Taka

Nobuo Nakamura

Hirofumi Yamashita

Ikuko Inoue

Tetsuya Yamaguchi

Yoshiro Baba

Hisanori Ihara

Hidetoshi Nozaki

Hidenori Shibata

Yoshiyuki Shioyama

Hideki Inokuma

Masako Hori

Hidenori Saihara

Akira Makabe

Seigo Abe

Koichi Kokubun

Koji Kimura

Hiroshi Takato

Hideaki Harakawa

Shizue Hori

Kuniaki Kumamaru

Tadaomi Sakurai

Kouji Kimura

Jiro Ohshima

Toshiyo Motozima

The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a pdiffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the pdiffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the pdiffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the pdiffusion layer to a position below the gate electrode.

Solid-state image pickup apparatus

The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p diffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the p diffusion layer to a position below the gate electrode.

In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Semiconductor device manufacturing method permitting suppression of leak current through the PN junction

Semiconductor device having a memory cell region and peripheral circuit region and method of manufacturing the same

According to a method of fabricating a selective epitaxial film, a thin insulating film serving as a mask is formed on the entire surface of a semiconductor substrate having a (100) plane. An opening portion reaching the semiconductor substrate is formed in a desired region of the thin insulating film. An epitaxial film is selectively grown in the opening portion. The semiconductor substrate having the selective epitaxial film formed thereon is annealed at at least a pressure of 1,000 Pa and at least a temperature of 800.degree. C. to fill a gap on the contact surface between the thin insulating film and the selective epitaxial film.

Method of forming selective epitaxial film

In a method of manufacturing a semiconductor device, to form an opening in an insulation film such as a silicon oxide on a semiconductor substrate in a reverse tapered sectional configuration such that no gap is formed between a side surface of an epitaxial growth layer formed in the opening and the opening in the insulation film, the insulation film having the opening is subjected to a thermal process in an atmosphere of non-oxidizing gas including hydrogen elements such as hydrogen, silane or disilane gas. An opening is formed in the insulation film on the semiconductor substrate using isotropic etching. As a result of the above-described thermal process, decomposition of a silicon oxide proceeds from the interface between the insulation film and the semiconductor substrate at a side-wall of the opening to eventually form the opening in a reverse tapered sectional configuration at least in an edge portion thereof.

Method of manufacturing semiconductor devices with a reverse tapered

A semiconductor device. A semiconductor substrate has a first conductivity. A first insulating layer is on the semiconductor substrate and has an opening so that a portion of the semiconductor substrate is exposed. A semiconductor layer has a second conductivity on the portion. A region in said semiconductor layer prevents a leakage current caused by a minute defect and faceting.

Epitaxial-base bipolar transistor

A semiconductor device and a method for manufacturing the same, in which a leak current generated in a pn junction formed between a silicon substrate and an epitaxial layer can be reduced. A silicon oxide film is formed on a silicon substrate having a (100) crystal plane. The silicon oxide film is patterned to form an opened portion and an inclined surface on a pattern edge of the silicon oxide film. The inclined surface forms an angle of 54.74.+-.5.degree. with the silicon substrate. An epitaxial layer is formed in the opened portion by selective epitaxial growth.

Semiconductor device and method for manufacturing the same

A groove is formed on a semiconductor substrate. A mask material layer is so formed on the surface of the semiconductor substrate as to open a groove region. With the mask material layer used as a mask, a semiconductor layer is selectively formed on the semiconductor substrate exposed with the inner wall surface of the groove. Then, the mask material layer is removed. An insulating film is formed on the semiconductor layer formed on the inner wall surface of the groove and the surface of the semiconductor substrate. The groove is buried with a conductor.

Method of manufacturing MOS type semiconductor device of vertical

In the Bi-CMOS process of manufacturing a semiconductor device by an effective combination of a bipolar transistor manufacturing process and a CMOS transistor manufacturing process in the case of the formation of a silicide film on a Bi-CMOS device, in which the bipolar transistor having an inner base region made of a silicon film grown by epitaxy and the MOS transistor having silicide formed on the gate electrode, source region and drain region in a self-aligned manner therewith are formed on the same semiconductor substrate, while the silicon film of the inner base region is epitaxially grown in a step, a silicon film is also epitaxially grown on the source/drain regions at the same time in the same step.

Process of manufacturing a semiconductor device

An N type diffusion layer as a collector is formed on a P type silicon substrate, and a field oxide film is formed on this diffusion layer. An MoSi.sub.2 film is formed on this field oxide film and a first opening is formed on those field oxide film and MoSi.sub.2 film to expose the diffusion layer. An N type layer is selectively epitaxially grown only on the bottom of the first opening. A base layer is formed on the N type layer, the side wall of the first opening and the MoSi.sub.2 film. The base layer on the N type layer is formed by epitaxial growth, while the base layer on the side wall of the first opening and the MoSi.sub.2 film is formed in a polycrystalline state. A first silicon oxide film is formed on this based layer. The first silicon oxide film is thinner on the polycrystalline base layer than on the epitaxially grown base layer. The first silicon oxide film is subjected to anisotropic etching to expose only the surface of the epitaxially grown base layer. An N type silicon film as an emitter is selectively grown only on this exposed base layer.

Method of fabricating a bipolar transistor operable at high speed

In a method of manufacturing a bonded semiconductor substrate, a SiGe mixed crystal layer, a silicon layer containing N-type impurities, a SiGe mixed crystal layer containing N-type impurities of high concentration, and a silicon layer containing N-type impurities of high concentration are formed in this order on a top surface of a silicon substrate by an epitaxial growth process to form a first semiconductor substrate. A silicon oxide film is formed on a surface of a silicon substrate to form a second semiconductor substrate. The first and second semiconductor substrates are bonded to each other by heat treatment, with their top surfaces contacting each other. The first semiconductor substrate is etched from the back surface thereof until the SiGe mixed crystal layer is exposed, and the SiGe mixed crystal layer is etched until the silicon layer containing N-type impurities is exposed. This method prevents the thickness of the element forming layer from varying.

Method of manufacturing a bonded semiconductor substrate and a

The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.

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Yokohama, Japan

Hiroshi Naruse