The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2004

Filed:

Mar. 19, 1999
Applicant:
Inventors:

Nobuo Nakamura, Yokohama, JP;

Hisanori Ihara, Yokohama, JP;

Ikuko Inoue, Kawasaki, JP;

Hidenori Shibata, Kawasaki, JP;

Akiko Nomachi, Yokohama, JP;

Yoshiyuki Shioyama, Kawasaki, JP;

Hidetoshi Nozaki, Yokohama, JP;

Masako Hori, Yokohama, JP;

Akira Makabe, Kawasaki, JP;

Hiroshi Naruse, Yokohama, JP;

Hideki Inokuma, Yokohama, JP;

Seigo Abe, Oita, JP;

Hirofumi Yamashita, Cambridge, MA (US);

Tetsuya Yamaguchi, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 3/14 ; H01L 2/9768 ;
U.S. Cl.
CPC ...
H04N 3/14 ; H01L 2/9768 ;
Abstract

The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p diffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the p diffusion layer to a position below the gate electrode.


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