Sagamihara, Japan

Hiroaki Nambu

This inventor holds 36 USPTO granted patents, primarily in Semiconductor Technology. Top assignees: Hitachi, Ltd., Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.. Active years: 1987-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroaki Nambu. Retrieved from https://idiyas.com/inventor/hiroaki-nambu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 69.4

Average Co-Inventor Count = 4.5

ph-index = 10

Forward Citations = 225(Granted Patents)


Location History:

  • Hachiouji, JP (1991)
  • Hachioji, JP (1987 - 1995)
  • Sagamihara, JP (1993 - 2010)

Company Filing History:


Years Active: 1987-2010

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Areas of Expertise:
Semiconductor Memory
Integrated Circuit
SCL Circuit
Timing Margin
Refresh Time
Noise Margin
Read Rate
Power Consumption
Clocked Logic Gate
Signal Transmission
High-Speed RAM
Memory Cell
36 patents (USPTO):Explore Patents

Title: Hiroaki Nambu - Innovator in Semiconductor Technology

Introduction

Hiroaki Nambu is a prominent inventor based in Sagamihara, Japan, known for his contributions to semiconductor technology. With a total of 36 patents to his name, he has significantly advanced the field by developing innovative semiconductor circuits that enhance performance and efficiency.

Latest Patents

Hiroaki Nambu's latest patents include groundbreaking inventions in semiconductor integrated circuits. One notable patent describes a semiconductor integrated circuit that generates an internal clock signal for fetching input data synchronously. This technology ensures that the timing margin is preserved even when the duty ratio of a clock signal deviates from 50%. The circuit features a clock input terminal for the clock signal, a data input terminal for the data signal, internal clock generating circuits, and a latch circuit that synchronizes the data signal to the internal clock.

Another significant patent involves a semiconductor memory device designed to improve yield by trimming the internal properties of a semiconductor device. This invention incorporates an internal voltage step-down circuit and an internal voltage step-up circuit that are adjustable, along with a fuse circuit unit and a JTAG function unit to optimize performance through logical operations.

Career Highlights

Throughout his career, Hiroaki Nambu has worked with esteemed companies such as Hitachi, Ltd. and Renesas Technology Corporation. His tenure at these organizations has allowed him to hone his expertise and lead innovative projects in semiconductor technology.

Collaborations

Nambu's work has often involved collaboration with fellow innovators. Notable coworkers include Kazuo Kanetani and Takeshi Kusunoki, with whom he has worked closely on various projects that have contributed to his impressive portfolio of patents.

Conclusion

Hiroaki Nambu's contributions to semiconductor technology have solidified his reputation as a leading inventor in the field. His latest innovations demonstrate a commitment to enhancing the performance and reliability of semiconductor devices, marking him as a significant figure in the ongoing advancements within this technology sector.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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