Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Device Engineering Co., Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hiroaki Nambu

Kazuo Kanetani

Takeshi Kusunoki

Kaname Yamasaki

Fumihiko Arakawa

Keiichi Higeta

Kunihiko Yamaguchi

Noriyuki Homma

Youji Idei

Kenichi Ohhata

Hisayuki Higuchi

Yoshiaki Sakurai

Hideto Kazama

Makoto Hanawa

Noboru Masuda

Kenji Kaneko

Shigeru Nakahara

Goro Kitsukawa

Takashi Uehara

Masanori Odaka

Toru Masuda

Masao Shinozaki

Takemi Negishi

Mamoru Takaku

Masahiro Yamashita

Jun Etoh

Isao Yoshida

Motoo Suwa

Tohru Nakamura

Nobuo Tamba

Yoji Idei

Toshiro Hiramoto

Yasuhiro Yoshikawa

Masayuki Ohayashi

Noriyuki Honma

Kayoko Saito

Kenichi Ohata

Takesi Kusunoki

Ken'ichi Ohata

A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Semiconductor integrated circuit which generates internal clock signal for fetching input data synchronously with the internal clock signal without decrease of timing margin

A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unitwhich inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.

Semiconductor memory device and semiconductor device

Semiconductor integrated circuit

Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.

Semiconductor device and system

A wiring board includes a plurality of wiring layers, and one surface formed with a plurality of chip connecting electrodes and another surface formed with a plurality of external connecting electrodes of a semiconductor device. The wiring board has wiring layers and vias. The plurality of chip connecting electrodes include first chip connecting electrodes, each used for a first signal whose logic value changes, and second chip connecting electrodes, each used for a second signal that changes after a change timing of the first signal. A wiring layer in which wiring routing of paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes is performed, and a wiring layer in which wiring routing of paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes is performed, are made different from each other.

Semiconductor device

A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.

Semiconductor memory device having short refresh time

To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit

It is an object of the invention to provide a circuit configuration wherein a decoder control signal &#x3a6;is rendered unnecessary between an address buffer control signal &#x3a6;and the decoder control signal &#x3a6;, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.

Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder

A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.

Semiconductor memory device

A high-speed, reduced power consumption address decoder circuit, wherein a decoder control signal &#x3a6;2 is rendered unnecessary between an address buffer control signal&#x3a6;1 and the decoder control signal &#x3a6;2, thereby implementing speed-up in operation of a decoder circuit. Improved speed and reduced power consumption are attained by a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.

Semiconductor device using SCL circuit

In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Method of testing a semiconductor integrated device

Growing community of inventors

Sagamihara, Japan

Hiroaki Nambu