Gregory M Schaeffer

USPTO Granted Patents = 26 (Patent Applications = 3)

Average Co-Inventor Count = 5.9

ph-index = 7

Forward Citations = 107(Granted Patents)

Location History:

Hinesburg, VT (US) (2007)
Poughkeepsie, NY (US) (2008 - 2021)

Company Filing History:

25 out of 164,108

International Business Machines Corporation

Years Active: 2007-2021

where 'Filed Patents' based on already Granted Patents

26 patents (USPTO):Sort by Forward Citations

Abstract keywords

1. 10902167 - Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits (2021-01-26),

2. 10831954 - Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs (2020-11-10),

3. 10691853 - Superposition of canonical timing value representations in statistical static timing analysis (2020-06-23),

4. 10606970 - Selection of corners and/or margins using statistical static timing analysis of an integrated circuit (2020-03-31),

5. 10380289 - Multi-sided variations for creating integrated circuits (2019-08-13),

6. 10380286 - Multi-sided variations for creating integrated circuits (2019-08-13),

7. 10346569 - Multi-sided variations for creating integrated circuits (2019-07-09),

8. 10289776 - Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit (2019-05-14),

9. 10169526 - Incremental parasitic extraction for coupled timing and power optimization (2019-01-01),

10. 10031985 - Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit (2018-07-24),

11. 10013516 - Selection of corners and/or margins using statistical static timing analysis of an integrated circuit (2018-07-03),

12. 9858383 - Incremental parasitic extraction for coupled timing and power optimization (2018-01-02),

13. 9767239 - Timing optimization driven by statistical sensitivites (2017-09-19),

14. 9754062 - Timing adjustments across transparent latches to facilitate power reduction (2017-09-05),

15. 9646122 - Variable accuracy parameter modeling in statistical timing (2017-05-09),

Title: Gregory M. Schaeffer – Innovator in Electronic Design Automation

Introduction

Gregory M. Schaeffer, based in Hinesburg, Vermont, is a prolific inventor with an impressive portfolio of 26 patents. His work primarily revolves around the domain of electronic design automation, significantly contributing to the optimization of digital integrated circuits.

Latest Patents

Among his latest notable patents, the first is titled "Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits." This invention focuses on enhancing the efficiency of electronic design automation by identifying transparent latches suitable for slack stealing within electronic logic circuit designs. The process involves assessing initial timing slack and determining whether this slack resides on a feedback path, optimizing performance accordingly.

Another recent patent is "Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs." This innovation increases efficiency by utilizing a data structure that represents hierarchical integrated circuit designs. It emphasizes optimizing sub-blocks based on default driving cells and electrical models, helping to achieve in-context closure for the designs.

Career Highlights

Gregory's professional journey includes significant tenures at renowned companies like IBM and Globalfoundries Inc. His endeavors at these organizations have propelled advancements in the field of electronic design automation, emphasizing the importance of optimizing design processes for better performance.

Collaborations

Throughout his career, Gregory has worked alongside notable colleagues such as Eric A. Foreman and Kerim Kalafala. Their collaborative efforts have contributed to many innovative solutions and advancements in the realm of integrated circuit design.

Conclusion

In summary, Gregory M. Schaeffer stands out as a key figure in the field of electronic design automation. With his extensive patent portfolio and contributions to leading technology companies, he continues to play a crucial role in advancing the efficiency and performance of digital integrated circuits.

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