The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Feb. 20, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Robert J. Allen, Jericho, VT (US);

Nathan C. Buck, Underhill, VT (US);

Eric A. Foreman, Fairfax, VT (US);

Jeffrey G. Hemmett, St. George, VT (US);

Kerim Kalafala, Rhinebeck, NY (US);

Gregory M. Schaeffer, Poughkeepsie, NY (US);

Stephen G. Shuma, Underhill, VT (US);

Debjit Sinha, Wappingers Falls, NY (US);

Natesan Venkateswaran, Hopewell Junction, NY (US);

Vladimir Zolotov, Putnam Valley, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 17/505 (2013.01); G06F 17/5022 (2013.01); G06F 17/5063 (2013.01); G06F 2217/84 (2013.01);
Abstract

The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.


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