International Business Machines Corporation

Globalfoundries Inc.

Gregory M Schaeffer

Eric A Foreman

Kerim Kalafala

Jeffrey G Hemmett

Stephen Gerard Shuma

Chandramouli Visweswariah

Vladimir P Zolotov

Natesan Venkateswaran

Nathan C Buck

Alexander Joel Suess

Michael H Wood

Debjit Sinha

David James Hathaway

Peter Anton Habitz

Robert J Allen

Adam P Matheny

David J Widiger

Jose Luis Neves

John P Dubuque

Brian M Dreibelbis

Soroush Abbaspour

Ravichander Ledalla

Tsz-mei Ko

Alice Hwajin Lee

Paul Gerard Villarrubia

Hemlata Gupta

Chandramouli V Kashyap

William John Livingstone

James Charles Gregerson

Adil Bhanji

Mark R Lasher

Ayesha Akhter

Chaitanya Ravindra Peddawad

Chaobo Li

Stephen G Shurma

Ravi Chander Ledalla

To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.

Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits

Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.

Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

Superposition of canonical timing value representations in statistical static timing analysis

Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Multi-sided variations for creating integrated circuits

Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Incremental parasitic extraction for coupled timing and power optimization

System and methods for achieving a timing closure in a design of an integrated circuit in presence of manufacturing variation. The method includes running a timing engine of a statistical timing analysis tool performing at least one optimization to fix at least one violation of at least one timing quantity at an integrated circuit location. The method includes choosing at least one optimization to apply and finding at least one failing timing quantity, where the quantity is failing due to at least one source of variability which the optimization would impact. The optimization is applied to at least one section of the path leading to the failing timing quantity, where the section contributes to the source of variability. Statistical sensitivity information in canonical form guides the optimization by providing a fully parameterized canonical form of the identified timing violations.

Timing optimization driven by statistical sensitivites

A method of implementing timing adjustments across a transparent latch of an integrated circuit, a system, and a computer program product are described. The method includes obtaining initial input timing slack and input potential power savings at an input and an initial output timing slack and output potential power savings at an output of the transparent latch. The method also includes adjusting a cycle boundary of the transparent latch to obtain a new input timing slack at the input and a new output timing slack at the output of the transparent latch, wherein the new input timing slack is greater than the initial input timing slack based on the input potential power savings being greater than the output potential power savings and the new output timing slack is greater than the initial output timing slack based on the output potential power savings being greater than the input potential power savings.

Timing adjustments across transparent latches to facilitate power reduction

Systems and methods compute a mean timing value of an integrated circuit design for variables using a first timing calculation of relatively higher accuracy; and calculate a first timing value of the integrated circuit design for the variables, using a second timing calculation having a relatively lower accuracy. Such systems and methods calculate second timing values of the integrated circuit design for additional sets of variables using the second timing calculation; and calculate finite differences of each of the second timing values to the first timing value. Thus, these systems and methods calculate a statistical sensitivity of the first timing value to the additional sets of variables based on the finite differences. Further, such systems and methods calculate a statistical sensitivity of the mean timing value to the additional sets of values based on the statistical sensitivity of the first timing value to the additional sets of values.

Variable accuracy parameter modeling in statistical timing

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Hinesburg, VT, United States of America

Gregory M Schaeffer